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Commit d1a082cc authored by Russell King's avatar Russell King Committed by Bjorn Helgaas
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PCI: mvebu: Remove code restricting accesses to slot 0 



Now that we advertise a PCIe capability, the Linux PCI layer will not scan
the bus for devices other than in slot 0.  This makes the work-around to
trap accesses to devices other than slot 0 unnecessary.

Tested-by: Willy Tarreau <w@1wt.eu> (Iomega iConnect Kirkwood, MiraBox Armada 370)
Tested-by: Andrew Lunn <andrew@lunn.ch> (D-Link DIR664 Kirkwood)
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
parent dc0352ab

drivers/pci/host/pci-mvebu.c

+0 −24
Original line number Original line Diff line number Diff line
@@ -794,17 +794,6 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 
	if (!mvebu_pcie_link_up(port))

	if (!mvebu_pcie_link_up(port))

		return PCIBIOS_DEVICE_NOT_FOUND;

		return PCIBIOS_DEVICE_NOT_FOUND;





	/*

	 * On the secondary bus, we don't want to expose any other

	 * device than the device physically connected in the PCIe

	 * slot, visible in slot 0. In slot 1, there's a special

	 * Marvell device that only makes sense when the Armada is

	 * used as a PCIe endpoint.

	 */

	if (bus->number == port->bridge.secondary_bus &&

	    PCI_SLOT(devfn) != 0)

		return PCIBIOS_DEVICE_NOT_FOUND;



	/* Access the real PCIe interface */

	/* Access the real PCIe interface */

	ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,

	ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,

				    where, size, val);

				    where, size, val);
@@ -835,19 +824,6 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 
		return PCIBIOS_DEVICE_NOT_FOUND;

		return PCIBIOS_DEVICE_NOT_FOUND;

	}

	}





	/*

	 * On the secondary bus, we don't want to expose any other

	 * device than the device physically connected in the PCIe

	 * slot, visible in slot 0. In slot 1, there's a special

	 * Marvell device that only makes sense when the Armada is

	 * used as a PCIe endpoint.

	 */

	if (bus->number == port->bridge.secondary_bus &&

	    PCI_SLOT(devfn) != 0) {

		*val = 0xffffffff;

		return PCIBIOS_DEVICE_NOT_FOUND;

	}



	/* Access the real PCIe interface */

	/* Access the real PCIe interface */

	ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,

	ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,

				    where, size, val);

				    where, size, val);