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Commit c0222ac0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "This is an unusually large pull request for MIPS - in parts because
  lots of patches missed the 3.18 deadline but primarily because some
  folks opened the flood gates.

   - Retire the MIPS-specific phys_t with the generic phys_addr_t.
   - Improvments for the backtrace code used by oprofile.
   - Better backtraces on SMP systems.
   - Cleanups for the Octeon platform code.
   - Cleanups and fixes for the Loongson platform code.
   - Cleanups and fixes to the firmware library.
   - Switch ATH79 platform to use the firmware library.
   - Grand overhault to the SEAD3 and Malta interrupt code.
   - Move the GIC interrupt code to drivers/irqchip
   - Lots of GIC cleanups and updates to the GIC code to use modern IRQ
     infrastructures and features of the kernel.
   - OF documentation updates for the GIC bindings
   - Move GIC clocksource driver to drivers/clocksource
   - Merge GIC clocksource driver with clockevent driver.
   - Further updates to bring the GIC clocksource driver up to date.
   - R3000 TLB code cleanups
   - Improvments to the Loongson 3 platform code.
   - Convert pr_warning to pr_warn.
   - Merge a bunch of small lantiq and ralink fixes that have been
     staged/lingering inside the openwrt tree for a while.
   - Update archhelp for IP22/IP32
   - Fix a number of issues for Loongson 1B.
   - New clocksource and clockevent driver for Loongson 1B.
   - Further work on clk handling for Loongson 1B.
   - Platform work for Broadcom BMIPS.
   - Error handling cleanups for TurboChannel.
   - Fixes and optimization to the microMIPS support.
   - Option to disable the FTLB.
   - Dump more relevant information on machine check exception
   - Change binfmt to allow arch to examine PT_*PROC headers
   - Support for new style FPU register model in O32
   - VDSO randomization.
   - BCM47xx cleanups
   - BCM47xx reimplement the way the kernel accesses NVRAM information.
   - Random cleanups
   - Add support for ATH25 platforms
   - Remove pointless locking code in some PCI platforms.
   - Some improvments to EVA support
   - Minor Alchemy cleanup"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits)
  MIPS: Add MFHC0 and MTHC0 instructions to uasm.
  MIPS: Cosmetic cleanups of page table headers.
  MIPS: Add CP0 macros for extended EntryLo registers
  MIPS: Remove now unused definition of phys_t.
  MIPS: Replace use of phys_t with phys_addr_t.
  MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT
  PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig.
  MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery
  MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO
  MIPS: <asm/types.h> fix indentation.
  MAINTAINERS: Add entry for BMIPS multiplatform kernel
  MIPS: Enable VDSO randomization
  MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration
  MIPS: Remove declaration of obsolete arch_init_clk_ops()
  MIPS: atomic.h: Reformat to fit in 79 columns
  MIPS: Apply `.insn' to fixup labels throughout
  MIPS: Fix microMIPS LL/SC immediate offsets
  MIPS: Kconfig: Only allow 32-bit microMIPS builds
  MIPS: signal.c: Fix an invalid cast in ISA mode bit handling
  MIPS: mm: Only build one microassembler that is suitable
  ...
parents 140cd7fb e2965cd0

Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt

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MIPS Global Interrupt Controller (GIC)



The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.

It also supports local (per-processor) interrupts and software-generated

interrupts which can be used as IPIs.  The GIC also includes a free-running

global timer, per-CPU count/compare timers, and a watchdog.



Required properties:

- compatible : Should be "mti,gic".

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt specifier.  Should be 3.

  - The first cell is the type of interrupt, local or shared.

    See <include/dt-bindings/interrupt-controller/mips-gic.h>.

  - The second cell is the GIC interrupt number.

  - The third cell encodes the interrupt flags.

    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid

    flags.



Optional properties:

- reg : Base address and length of the GIC registers.  If not present,

  the base address reported by the hardware GCR_GIC_BASE will be used.

- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors

  to which the GIC may not route interrupts.  Valid values are 2 - 7.

  This property is ignored if the CPU is started in EIC mode.



Required properties for timer sub-node:

- compatible : Should be "mti,gic-timer".

- interrupts : Interrupt for the GIC local timer.

- clock-frequency : Clock frequency at which the GIC timers operate.



Example:



	gic: interrupt-controller@1bdc0000 {

		compatible = "mti,gic";

		reg = <0x1bdc0000 0x20000>;



		interrupt-controller;

		#interrupt-cells = <3>;



		mti,reserved-cpu-vectors = <7>;



		timer {

			compatible = "mti,gic-timer";

			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;

			clock-frequency = <50000000>;

		};

	};



	uart@18101400 {

		...

		interrupt-parent = <&gic>;

		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;

		...

	};

Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt

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* Interrupt Controller



Properties:

- compatible: "brcm,bcm3384-intc"



  Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs.



- reg: Address/length pairs for each mask/status register set.  Length must

  be 8.  If multiple register sets are specified, the first set will

  handle IRQ offsets 0..31, the second set 32..63, and so on.



- interrupt-controller: This is an interrupt controller.



- #interrupt-cells: Must be <1>.  Just a simple IRQ offset; no level/edge

  or polarity configuration is possible with this controller.



- interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or

  from another INTC.



- interrupts: The IRQ on the parent controller.



Example:

	periph_intc: periph_intc@14e00038 {

		compatible = "brcm,bcm3384-intc";



		/*

		 * IRQs 0..31:  mask reg 0x14e00038, status reg 0x14e0003c

		 * IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344

		 */

		reg = <0x14e00038 0x8 0x14e00340 0x8>;



		interrupt-controller;

		#interrupt-cells = <1>;



		interrupt-parent = <&cpu_intc>;

		interrupts = <4>;

	};

Documentation/devicetree/bindings/mips/brcm/bmips.txt

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* Broadcom MIPS (BMIPS) CPUs



Required properties:

- compatible: "brcm,bmips3300", "brcm,bmips4350", "brcm,bmips4380",

  "brcm,bmips5000"



- mips-hpt-frequency: This is common to all CPUs in the system so it lives

  under the "cpus" node.

Documentation/devicetree/bindings/mips/brcm/cm-dsl.txt

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* Broadcom cable/DSL platforms



SoCs:



Required properties:

- compatible: "brcm,bcm3384", "brcm,bcm33843"



Boards:



Required properties:

- compatible: "brcm,bcm93384wvg"

Documentation/devicetree/bindings/mips/brcm/usb.txt

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* Broadcom USB controllers



Required properties:

- compatible: "brcm,bcm3384-ohci", "brcm,bcm3384-ehci"



  These currently use the generic-ohci and generic-ehci drivers.  On some

  systems, special handling may be needed in the following cases:



  - Restoring state after systemwide power save modes

  - Sharing PHYs with the USBD (UDC) hardware

  - Figuring out which controllers are disabled on ASIC bondout variants