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Commit e2965cd0 authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
Browse files

MIPS: Add MFHC0 and MTHC0 instructions to uasm. 



New instructions for Extended Physical Addressing (XPA) functionality.

Signed-off-by: default avatarSteven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8453/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 77a5c593

arch/mips/include/asm/uasm.h

+2 −0
Original line number Diff line number Diff line
@@ -136,9 +136,11 @@ Ip_u1s2(_lui); 
Ip_u2s3u1(_lw);

Ip_u3u1u2(_lwx);

Ip_u1u2u3(_mfc0);

Ip_u1u2u3(_mfhc0);

Ip_u1(_mfhi);

Ip_u1(_mflo);

Ip_u1u2u3(_mtc0);

Ip_u1u2u3(_mthc0);

Ip_u3u1u2(_mul);

Ip_u3u1u2(_or);

Ip_u2u1u3(_ori);

arch/mips/include/uapi/asm/inst.h

+4 −3
Original line number Diff line number Diff line
@@ -108,9 +108,10 @@ enum rt_op { 
 */

enum cop_op {

	mfc_op	      = 0x00, dmfc_op	    = 0x01,

	cfc_op	      = 0x02, mfhc_op	    = 0x03,

	mtc_op        = 0x04, dmtc_op	    = 0x05,

	ctc_op	      = 0x06, mthc_op	    = 0x07,

	cfc_op	      = 0x02, mfhc0_op	    = 0x02,

	mfhc_op       = 0x03, mtc_op	    = 0x04,

	dmtc_op	      = 0x05, ctc_op	    = 0x06,

	mthc0_op      = 0x06, mthc_op	    = 0x07,

	bc_op	      = 0x08, cop_op	    = 0x10,

	copm_op	      = 0x18

};

arch/mips/mm/uasm-mips.c

+2 −0
Original line number Diff line number Diff line
@@ -96,9 +96,11 @@ static struct insn insn_table[] = { 
	{ insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },

	{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },

	{ insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mfhc0,  M(cop0_op, mfhc0_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mfhi,  M(spec_op, 0, 0, 0, 0, mfhi_op), RD },

	{ insn_mflo,  M(spec_op, 0, 0, 0, 0, mflo_op), RD },

	{ insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mthc0,  M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},

	{ insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},

	{ insn_ori,  M(ori_op, 0, 0, 0, 0, 0),	RS | RT | UIMM },

	{ insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },

arch/mips/mm/uasm.c

+8 −6
Original line number Diff line number Diff line
@@ -51,12 +51,12 @@ enum opcode { 
	insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,

	insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,

	insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,

	insn_lwx, insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul,

	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,

	insn_sd, insn_sll, insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra,

	insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,

	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,

	insn_xor, insn_xori, insn_yield,

	insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,

	insn_mthc0, insn_mul, insn_or, insn_ori, insn_pref, insn_rfe,

	insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_slt,

	insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu,

	insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi,

	insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield,

};



struct insn {
@@ -284,9 +284,11 @@ I_u2s3u1(_lld) 
I_u1s2(_lui)

I_u2s3u1(_lw)

I_u1u2u3(_mfc0)

I_u1u2u3(_mfhc0)

I_u1(_mfhi)

I_u1(_mflo)

I_u1u2u3(_mtc0)

I_u1u2u3(_mthc0)

I_u3u1u2(_mul)

I_u2u1u3(_ori)

I_u3u1u2(_or)