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Commit c007b3a6 authored by Uwe Kleine-König's avatar Uwe Kleine-König Committed by Shawn Guo
Browse files

ARM: dts: imx6qdl: don't configure reserved pad settings 



Several dts files set a bit in the SPEED field for pads
RGMII_{R,T}{XC,D0,D1,D2,D3,X_CTL}, but that doesn't exist. Writing there
doesn't have an effect and the bit reads as zero.

Signed-off-by: default avatarUwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 51a012b7

arch/arm/boot/dts/imx6dl-riotboard.dts

+11 −11
Original line number Diff line number Diff line
@@ -376,18 +376,18 @@ 
			fsl,pins = <

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1		/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0		/* AR8035 pin strapping: IO voltage: pull up */

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x130b0		/* AR8035 pin strapping: PHYADDR#0: pull down */

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x130b0		/* AR8035 pin strapping: PHYADDR#1: pull down */

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0		/* AR8035 pin strapping: MODE#1: pull up */

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0		/* AR8035 pin strapping: MODE#3: pull up */

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030		/* AR8035 pin strapping: IO voltage: pull up */

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030		/* AR8035 pin strapping: PHYADDR#0: pull down */

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030		/* AR8035 pin strapping: PHYADDR#1: pull down */

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030		/* AR8035 pin strapping: MODE#1: pull up */

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030		/* AR8035 pin strapping: MODE#3: pull up */

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x130b0		/* AR8035 pin strapping: MODE#0: pull down */

				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8	/* GPIO16 -> AR8035 25MHz */

			        MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x130b0		/* RGMII_nRST */

arch/arm/boot/dts/imx6q-arm2.dts

+12 −12
Original line number Diff line number Diff line
@@ -79,19 +79,19 @@ 
			fsl,pins = <

				MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030

				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1

			>;

		};

arch/arm/boot/dts/imx6q-ba16.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -448,19 +448,19 @@ 
		fsl,pins = <

			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x100b0

			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x100b0

			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x100b0

			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x100b0

			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x100b0

			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x100b0

			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x100b0

			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0

			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x10030

			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x10030

			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x10030

			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x10030

			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x10030

			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030

			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x100b0

			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0

			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0

			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0

			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0

			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0

			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0

			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030

			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030

			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030

			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030

			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030

			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030

			/* FEC Reset */

			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28     0x1b0b0

			/* AR8033 Interrupt */

arch/arm/boot/dts/imx6q-cm-fx6.dts

+12 −12
Original line number Diff line number Diff line
@@ -168,18 +168,18 @@ 


	pinctrl_enet: enetgrp {

		fsl,pins = <

			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030

			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030

			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030

			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030

			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030

			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030

			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030

			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030

			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030

			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030

			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030

			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030

			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts

+12 −12
Original line number Diff line number Diff line
@@ -324,18 +324,18 @@ 


		pinctrl_enet: enetgrp {

			fsl,pins = <

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0