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Commit bb195016 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'qcom-dt-for-3.16-2' of... 

Merge tag 'qcom-dt-for-3.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/dt

Merge "Qualcomm ARM Based Device Tree Updates for v3.16-2" from Kumar Gala:

* Updated MSM8660/MSM8960/MSM8974 dts for various updates or conformitity
  to binding specs
* Added APQ8064 SoC and IFC6410 board device tree support
* Added APQ8084 SoC and APQ8084-MTP board device tree support

* tag 'qcom-dt-for-3.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom

:
  ARM: dts: qcom: Add APQ8084-MTP board support
  ARM: dts: qcom: Add APQ8084 SoC support
  ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees
  ARM: dts: qcom: Update msm8660 device trees
  ARM: dts: qcom: Update msm8960 device trees
  ARM: dts: qcom: Update msm8974/apq8074 device trees

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents e1134cb6 f46d23f6

arch/arm/boot/dts/Makefile

+6 −3
Original line number Diff line number Diff line
@@ -308,9 +308,12 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ 
	orion5x-maxtor-shared-storage-2.dtb \

	orion5x-rd88f5182-nas.dtb

dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb

dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \

	qcom-msm8960-cdp.dtb \

	qcom-apq8074-dragonboard.dtb

dtb-$(CONFIG_ARCH_QCOM) += \

	qcom-apq8064-ifc6410.dtb \

	qcom-apq8074-dragonboard.dtb \

	qcom-apq8084-mtp.dtb \

	qcom-msm8660-surf.dtb \

	qcom-msm8960-cdp.dtb

dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb

dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \

	s3c6410-smdk6410.dtb

arch/arm/boot/dts/qcom-apq8064-ifc6410.dts

0 → 100644
+16 −0
Original line number Diff line number Diff line 
#include "qcom-apq8064-v2.0.dtsi"



/ {

	model = "Qualcomm APQ8064/IFC6410";

	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";



	soc {

		gsbi@16600000 {

			status = "ok";

			qcom,mode = <GSBI_PROT_I2C_UART>;

			serial@16640000 {

				status = "ok";

			};

		};

	};

};

arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi

0 → 100644
+1 −0
Original line number Diff line number Diff line 
#include "qcom-apq8064.dtsi"

arch/arm/boot/dts/qcom-apq8064.dtsi

0 → 100644
+170 −0
Original line number Diff line number Diff line 
/dts-v1/;



#include "skeleton.dtsi"

#include <dt-bindings/clock/qcom,gcc-msm8960.h>

#include <dt-bindings/soc/qcom,gsbi.h>



/ {

	model = "Qualcomm APQ8064";

	compatible = "qcom,apq8064";

	interrupt-parent = <&intc>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "qcom,krait";

			enable-method = "qcom,kpss-acc-v1";

			device_type = "cpu";

			reg = <0>;

			next-level-cache = <&L2>;

			qcom,acc = <&acc0>;

			qcom,saw = <&saw0>;

		};



		cpu@1 {

			compatible = "qcom,krait";

			enable-method = "qcom,kpss-acc-v1";

			device_type = "cpu";

			reg = <1>;

			next-level-cache = <&L2>;

			qcom,acc = <&acc1>;

			qcom,saw = <&saw1>;

		};



		cpu@2 {

			compatible = "qcom,krait";

			enable-method = "qcom,kpss-acc-v1";

			device_type = "cpu";

			reg = <2>;

			next-level-cache = <&L2>;

			qcom,acc = <&acc2>;

			qcom,saw = <&saw2>;

		};



		cpu@3 {

			compatible = "qcom,krait";

			enable-method = "qcom,kpss-acc-v1";

			device_type = "cpu";

			reg = <3>;

			next-level-cache = <&L2>;

			qcom,acc = <&acc3>;

			qcom,saw = <&saw3>;

		};



		L2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

		};

	};



	cpu-pmu {

		compatible = "qcom,krait-pmu";

		interrupts = <1 10 0x304>;

	};



	soc: soc {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		compatible = "simple-bus";



		intc: interrupt-controller@2000000 {

			compatible = "qcom,msm-qgic2";

			interrupt-controller;

			#interrupt-cells = <3>;

			reg = <0x02000000 0x1000>,

			      <0x02002000 0x1000>;

		};



		timer@200a000 {

			compatible = "qcom,kpss-timer", "qcom,msm-timer";

			interrupts = <1 1 0x301>,

				     <1 2 0x301>,

				     <1 3 0x301>;

			reg = <0x0200a000 0x100>;

			clock-frequency = <27000000>,

					  <32768>;

			cpu-offset = <0x80000>;

		};



		acc0: clock-controller@2088000 {

			compatible = "qcom,kpss-acc-v1";

			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;

		};



		acc1: clock-controller@2098000 {

			compatible = "qcom,kpss-acc-v1";

			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;

		};



		acc2: clock-controller@20a8000 {

			compatible = "qcom,kpss-acc-v1";

			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;

		};



		acc3: clock-controller@20b8000 {

			compatible = "qcom,kpss-acc-v1";

			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;

		};



		saw0: regulator@2089000 {

			compatible = "qcom,saw2";

			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;

			regulator;

		};



		saw1: regulator@2099000 {

			compatible = "qcom,saw2";

			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;

			regulator;

		};



		saw2: regulator@20a9000 {

			compatible = "qcom,saw2";

			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;

			regulator;

		};



		saw3: regulator@20b9000 {

			compatible = "qcom,saw2";

			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;

			regulator;

		};



		gsbi7: gsbi@16600000 {

			status = "disabled";

			compatible = "qcom,gsbi-v1.0.0";

			reg = <0x16600000 0x100>;

			clocks = <&gcc GSBI7_H_CLK>;

			clock-names = "iface";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			serial@16640000 {

				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

				reg = <0x16640000 0x1000>,

				      <0x16600000 0x1000>;

				interrupts = <0 158 0x0>;

				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;

				clock-names = "core", "iface";

				status = "disabled";

			};

		};



		qcom,ssbi@500000 {

			compatible = "qcom,ssbi";

			reg = <0x00500000 0x1000>;

			qcom,controller-type = "pmic-arbiter";

		};



		gcc: clock-controller@900000 {

			compatible = "qcom,gcc-apq8064";

			reg = <0x00900000 0x4000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

		};

	};

};

arch/arm/boot/dts/qcom-apq8074-dragonboard.dts

+27 −1
Original line number Diff line number Diff line
@@ -4,7 +4,11 @@ 
	model = "Qualcomm APQ8074 Dragonboard";

	compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";



	soc: soc {

	soc {

		serial@f991e000 {

			status = "ok";

		};



		sdhci@f9824900 {

			bus-width = <8>;

			non-removable;
@@ -15,5 +19,27 @@ 
			cd-gpios = <&msmgpio 62 0x1>;

			bus-width = <4>;

		};





		pinctrl@fd510000 {

			spi8_default: spi8_default {

				mosi {

					pins = "gpio45";

					function = "blsp_spi8";

				};

				miso {

					pins = "gpio46";

					function = "blsp_spi8";

				};

				cs {

					pins = "gpio47";

					function = "blsp_spi8";

				};

				clk {

					pins = "gpio48";

					function = "blsp_spi8";

				};

			};

		};

	};

};