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Commit e1134cb6 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'omap-for-v3.16/dt-part3' of... 

Merge tag 'omap-for-v3.16/dt-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Merge "omap dt fixes and and clocks for v3.16 merge window" from Tony Lindgren:

Most likely the last pull request from me for omap changes for
v3.16 that's dts fixes for clocks and enabling few features
that were still being discussed earlier:

- A bunch of omap clock related dts fixes queued by Tero Kristo.

- Enable parallel nand on am437x that was not merged earlier as
  I requested more information about the muxing for it. And
  we need to also enable ecc hardware support for am43xx.

- Enable the modem support for n900 that was dropped earlier
  because we had to fix the related hwmod entry first with patch
  ARM: OMAP2+: Fix ssi hwmod entry to allow idling.

- And finally, add the omap2 clock dts files. These will allow
  us to enable the dt clocks and drop the legacy clocks for omap2
  with a follow-up patch once the related clock driver binding
  changes are merged.

* tag 'omap-for-v3.16/dt-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

:
  ARM: dts: omap2 clock data
  ARM: dts: am437x-gp-evm: add support for parallel NAND flash
  ARM: OMAP2+: gpmc: enable BCH_HW ecc-scheme for AM43xx platforms
  ARM: dts: omap3 a83x: fix duplicate usb pin config
  ARM: dts: omap3: set mcbsp2 status
  ARM: dts: omap3-n900: Add modem support
  ARM: dts: omap3-n900: Add SSI support
  ARM: OMAP2+: Fix ssi hwmod entry to allow idling
  ARM: dts: AM4372: clk: efuse based crystal frequency detect
  ARM: dts: am43xx-clocks.dtsi: add ti, set-rate-parent to display clock path
  ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clk
  ARM: dts: omap4: add twd clock to DT
  ARM: dts: omap54xx-clocks: Correct abe_iclk clock node
  ARM: dts: omap54xx-clocks: remove the autoidle properties for clock nodes
  ARM: dts: am43x-clock: add tbclk data for ehrpwm
  ARM: dts: am33xx-clock: Fix ehrpwm tbclk data
  ARM: dts: set 'ti,set-rate-parent' for dpll4_m5 path
  ARM: dts: use ti,fixed-factor-clock for dpll4_m5x2_mul_ck
  ARM: dts: am43xx-clocks: use ti, fixed-factor-clock for dpll_per_clkdcoldo

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 81d1d392 43369f0f

arch/arm/boot/dts/am33xx-clocks.dtsi

+6 −24
Original line number Diff line number Diff line
@@ -96,47 +96,29 @@ 
		clock-div = <1>;

	};



	ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {

	ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,composite-no-wait-gate-clock";

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <0>;

		reg = <0x0664>;

	};



	ehrpwm0_tbclk: ehrpwm0_tbclk {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&ehrpwm0_gate_tbclk>;

	};



	ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {

	ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,composite-no-wait-gate-clock";

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <1>;

		reg = <0x0664>;

	};



	ehrpwm1_tbclk: ehrpwm1_tbclk {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&ehrpwm1_gate_tbclk>;

	};



	ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {

	ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,composite-no-wait-gate-clock";

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <2>;

		reg = <0x0664>;

	};



	ehrpwm2_tbclk: ehrpwm2_tbclk {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&ehrpwm2_gate_tbclk>;

	};

};

&prcm_clocks {

	clk_32768_ck: clk_32768_ck {

arch/arm/boot/dts/am437x-gp-evm.dts

+108 −0
Original line number Diff line number Diff line
@@ -150,6 +150,27 @@ 
			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)

		>;

	};



	nand_flash_x8: nand_flash_x8 {

		pinctrl-single,pins = <

			0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* spi2_cs0.gpio/eMMCorNANDsel */

			0x0  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */

			0x4  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */

			0x8  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */

			0xc  (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */

			0x10 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */

			0x14 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */

			0x18 (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */

			0x1c (PIN_INPUT  | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */

			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */

			0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */

			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */

			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */

			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */

			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */

			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */

		>;

	};

};



&i2c0 {
@@ -246,3 +267,90 @@ 
	phy_id = <&davinci_mdio>, <0>;

	phy-mode = "rgmii";

};



&elm {

	status = "okay";

};



&gpmc {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&nand_flash_x8>;

	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */

	nand@0,0 {

		reg = <0 0 4>;		/* device IO registers */

		ti,nand-ecc-opt = "bch8";

		ti,elm-id = <&elm>;

		nand-bus-width = <8>;

		gpmc,device-width = <1>;

		gpmc,sync-clk-ps = <0>;

		gpmc,cs-on-ns = <0>;

		gpmc,cs-rd-off-ns = <40>;

		gpmc,cs-wr-off-ns = <40>;

		gpmc,adv-on-ns = <0>;

		gpmc,adv-rd-off-ns = <25>;

		gpmc,adv-wr-off-ns = <25>;

		gpmc,we-on-ns = <0>;

		gpmc,we-off-ns = <20>;

		gpmc,oe-on-ns = <3>;

		gpmc,oe-off-ns = <30>;

		gpmc,access-ns = <30>;

		gpmc,rd-cycle-ns = <40>;

		gpmc,wr-cycle-ns = <40>;

		gpmc,wait-pin = <0>;

		gpmc,wait-on-read;

		gpmc,wait-on-write;

		gpmc,bus-turnaround-ns = <0>;

		gpmc,cycle2cycle-delay-ns = <0>;

		gpmc,clk-activation-ns = <0>;

		gpmc,wait-monitoring-ns = <0>;

		gpmc,wr-access-ns = <40>;

		gpmc,wr-data-mux-bus-ns = <0>;

		/* MTD partition table */

		/* All SPL-* partitions are sized to minimal length

		 * which can be independently programmable. For

		 * NAND flash this is equal to size of erase-block */

		#address-cells = <1>;

		#size-cells = <1>;

		partition@0 {

			label = "NAND.SPL";

			reg = <0x00000000 0x00040000>;

		};

		partition@1 {

			label = "NAND.SPL.backup1";

			reg = <0x00040000 0x00040000>;

		};

		partition@2 {

			label = "NAND.SPL.backup2";

			reg = <0x00080000 0x00040000>;

		};

		partition@3 {

			label = "NAND.SPL.backup3";

			reg = <0x000c0000 0x00040000>;

		};

		partition@4 {

			label = "NAND.u-boot-spl-os";

			reg = <0x00100000 0x00080000>;

		};

		partition@5 {

			label = "NAND.u-boot";

			reg = <0x00180000 0x00100000>;

		};

		partition@6 {

			label = "NAND.u-boot-env";

			reg = <0x00280000 0x00040000>;

		};

		partition@7 {

			label = "NAND.u-boot-env.backup1";

			reg = <0x002c0000 0x00040000>;

		};

		partition@8 {

			label = "NAND.kernel";

			reg = <0x00300000 0x00700000>;

		};

		partition@9 {

			label = "NAND.file-system";

			reg = <0x00a00000 0x1f600000>;

		};

	};

};

arch/arm/boot/dts/am43xx-clocks.dtsi

+72 −3
Original line number Diff line number Diff line
@@ -9,6 +9,22 @@ 
 */

&scrm_clocks {

	sys_clkin_ck: sys_clkin_ck {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;

		ti,bit-shift = <31>;

		reg = <0x0040>;

	};



	crystal_freq_sel_ck: crystal_freq_sel_ck {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;

		ti,bit-shift = <29>;

		reg = <0x0040>;

	};



	sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -87,6 +103,54 @@ 
		clock-mult = <1>;

		clock-div = <1>;

	};



	ehrpwm0_tbclk: ehrpwm0_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <0>;

		reg = <0x0664>;

	};



	ehrpwm1_tbclk: ehrpwm1_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <1>;

		reg = <0x0664>;

	};



	ehrpwm2_tbclk: ehrpwm2_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <2>;

		reg = <0x0664>;

	};



	ehrpwm3_tbclk: ehrpwm3_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <4>;

		reg = <0x0664>;

	};



	ehrpwm4_tbclk: ehrpwm4_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <5>;

		reg = <0x0664>;

	};



	ehrpwm5_tbclk: ehrpwm5_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		ti,bit-shift = <6>;

		reg = <0x0664>;

	};

};

&prcm_clocks {

	clk_32768_ck: clk_32768_ck {
@@ -229,6 +293,7 @@ 
		reg = <0x2e30>;

		ti,index-starts-at-one;

		ti,invert-autoidle-bit;

		ti,set-rate-parent;

	};



	dpll_per_ck: dpll_per_ck {
@@ -511,6 +576,7 @@ 
		compatible = "ti,mux-clock";

		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;

		reg = <0x4244>;

		ti,set-rate-parent;

	};



	dpll_extdev_ck: dpll_extdev_ck {
@@ -609,10 +675,13 @@ 


	dpll_per_clkdcoldo: dpll_per_clkdcoldo {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		compatible = "ti,fixed-factor-clock";

		clocks = <&dpll_per_ck>;

		clock-mult = <1>;

		clock-div = <1>;

		ti,clock-mult = <1>;

		ti,clock-div = <1>;

		ti,autoidle-shift = <8>;

		reg = <0x2e14>;

		ti,invert-autoidle-bit;

	};



	dll_aging_clk_div: dll_aging_clk_div {

arch/arm/boot/dts/omap2420-clocks.dtsi

0 → 100644
+270 −0
Original line number Diff line number Diff line 
/*

 * Device Tree Source for OMAP2420 clock data

 *

 * Copyright (C) 2014 Texas Instruments, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



&prcm_clocks {

	sys_clkout2_src_gate: sys_clkout2_src_gate {

		#clock-cells = <0>;

		compatible = "ti,composite-no-wait-gate-clock";

		clocks = <&core_ck>;

		ti,bit-shift = <15>;

		reg = <0x0070>;

	};



	sys_clkout2_src_mux: sys_clkout2_src_mux {

		#clock-cells = <0>;

		compatible = "ti,composite-mux-clock";

		clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;

		ti,bit-shift = <8>;

		reg = <0x0070>;

	};



	sys_clkout2_src: sys_clkout2_src {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;

	};



	sys_clkout2: sys_clkout2 {

		#clock-cells = <0>;

		compatible = "ti,divider-clock";

		clocks = <&sys_clkout2_src>;

		ti,bit-shift = <11>;

		ti,max-div = <64>;

		reg = <0x0070>;

		ti,index-power-of-two;

	};



	dsp_gate_ick: dsp_gate_ick {

		#clock-cells = <0>;

		compatible = "ti,composite-interface-clock";

		clocks = <&dsp_fck>;

		ti,bit-shift = <1>;

		reg = <0x0810>;

	};



	dsp_div_ick: dsp_div_ick {

		#clock-cells = <0>;

		compatible = "ti,composite-divider-clock";

		clocks = <&dsp_fck>;

		ti,bit-shift = <5>;

		ti,max-div = <3>;

		reg = <0x0840>;

		ti,index-starts-at-one;

	};



	dsp_ick: dsp_ick {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&dsp_gate_ick>, <&dsp_div_ick>;

	};



	iva1_gate_ifck: iva1_gate_ifck {

		#clock-cells = <0>;

		compatible = "ti,composite-gate-clock";

		clocks = <&core_ck>;

		ti,bit-shift = <10>;

		reg = <0x0800>;

	};



	iva1_div_ifck: iva1_div_ifck {

		#clock-cells = <0>;

		compatible = "ti,composite-divider-clock";

		clocks = <&core_ck>;

		ti,bit-shift = <8>;

		reg = <0x0840>;

		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;

	};



	iva1_ifck: iva1_ifck {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;

	};



	iva1_ifck_div: iva1_ifck_div {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&iva1_ifck>;

		clock-mult = <1>;

		clock-div = <2>;

	};



	iva1_mpu_int_ifck: iva1_mpu_int_ifck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&iva1_ifck_div>;

		ti,bit-shift = <8>;

		reg = <0x0800>;

	};



	wdt3_ick: wdt3_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&l4_ck>;

		ti,bit-shift = <28>;

		reg = <0x0210>;

	};



	wdt3_fck: wdt3_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&func_32k_ck>;

		ti,bit-shift = <28>;

		reg = <0x0200>;

	};



	mmc_ick: mmc_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&l4_ck>;

		ti,bit-shift = <26>;

		reg = <0x0210>;

	};



	mmc_fck: mmc_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&func_96m_ck>;

		ti,bit-shift = <26>;

		reg = <0x0200>;

	};



	eac_ick: eac_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&l4_ck>;

		ti,bit-shift = <24>;

		reg = <0x0210>;

	};



	eac_fck: eac_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&func_96m_ck>;

		ti,bit-shift = <24>;

		reg = <0x0200>;

	};



	i2c1_fck: i2c1_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&func_12m_ck>;

		ti,bit-shift = <19>;

		reg = <0x0200>;

	};



	i2c2_fck: i2c2_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&func_12m_ck>;

		ti,bit-shift = <20>;

		reg = <0x0200>;

	};



	vlynq_ick: vlynq_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&core_l3_ck>;

		ti,bit-shift = <3>;

		reg = <0x0210>;

	};



	vlynq_gate_fck: vlynq_gate_fck {

		#clock-cells = <0>;

		compatible = "ti,composite-gate-clock";

		clocks = <&core_ck>;

		ti,bit-shift = <3>;

		reg = <0x0200>;

	};



	core_d18_ck: core_d18_ck {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&core_ck>;

		clock-mult = <1>;

		clock-div = <18>;

	};



	vlynq_mux_fck: vlynq_mux_fck {

		#clock-cells = <0>;

		compatible = "ti,composite-mux-clock";

		clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;

		ti,bit-shift = <15>;

		reg = <0x0240>;

	};



	vlynq_fck: vlynq_fck {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;

	};

};



&prcm_clockdomains {

	gfx_clkdm: gfx_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&gfx_ick>;

	};



	core_l3_clkdm: core_l3_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;

	};



	wkup_clkdm: wkup_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,

			 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,

			 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;

	};



	iva1_clkdm: iva1_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&iva1_mpu_int_ifck>;

	};



	dss_clkdm: dss_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&dss_ick>, <&dss_54m_fck>;

	};



	core_l4_clkdm: core_l4_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,

			 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,

			 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,

			 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,

			 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,

			 <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,

			 <&uart3_ick>, <&uart3_fck>, <&cam_ick>,

			 <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,

			 <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,

			 <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,

			 <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,

			 <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,

			 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,

			 <&pka_ick>;

	};

};



&func_96m_ck {

	compatible = "fixed-factor-clock";

	clocks = <&apll96_ck>;

	clock-mult = <1>;

	clock-div = <1>;

};



&dsp_div_fck {

	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;

};



&ssi_ssr_sst_div_fck {

	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;

};

arch/arm/boot/dts/omap2420.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -14,6 +14,32 @@ 
	compatible = "ti,omap2420", "ti,omap2";



	ocp {

		prcm: prcm@48008000 {

			compatible = "ti,omap2-prcm";

			reg = <0x48008000 0x1000>;



			prcm_clocks: clocks {

				#address-cells = <1>;

				#size-cells = <0>;

			};



			prcm_clockdomains: clockdomains {

			};

		};



		scrm: scrm@48000000 {

			compatible = "ti,omap2-scrm";

			reg = <0x48000000 0x1000>;



			scrm_clocks: clocks {

				#address-cells = <1>;

				#size-cells = <0>;

			};



			scrm_clockdomains: clockdomains {

			};

		};



		counter32k: counter@48004000 {

			compatible = "ti,omap-counter32k";

			reg = <0x48004000 0x20>;