Loading arch/arm/boot/dts/am4372.dtsi +5 −2 Original line number Diff line number Diff line Loading @@ -549,8 +549,11 @@ #address-cells = <1>; #size-cells = <1>; ti,hwmods = "cpgmac0"; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; clock-names = "fck", "cpts"; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, <&dpll_clksel_mac_clk>; clock-names = "fck", "cpts", "50mclk"; assigned-clocks = <&dpll_clksel_mac_clk>; assigned-clock-rates = <50000000>; status = "disabled"; cpdma_channels = <8>; ale_entries = <1024>; Loading arch/arm/boot/dts/am43xx-clocks.dtsi +9 −0 Original line number Diff line number Diff line Loading @@ -486,6 +486,15 @@ reg = <0x4238>; }; dpll_clksel_mac_clk: dpll_clksel_mac_clk { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5_ck>; reg = <0x4234>; ti,bit-shift = <2>; ti,dividers = <2>, <5>; }; clk_32k_mosc_ck: clk_32k_mosc_ck { #clock-cells = <0>; compatible = "fixed-clock"; Loading drivers/clk/ti/clk-43xx.c +1 −0 Original line number Diff line number Diff line Loading @@ -71,6 +71,7 @@ static struct ti_dt_clk am43xx_clks[] = { DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"), DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), Loading Loading
arch/arm/boot/dts/am4372.dtsi +5 −2 Original line number Diff line number Diff line Loading @@ -549,8 +549,11 @@ #address-cells = <1>; #size-cells = <1>; ti,hwmods = "cpgmac0"; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; clock-names = "fck", "cpts"; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, <&dpll_clksel_mac_clk>; clock-names = "fck", "cpts", "50mclk"; assigned-clocks = <&dpll_clksel_mac_clk>; assigned-clock-rates = <50000000>; status = "disabled"; cpdma_channels = <8>; ale_entries = <1024>; Loading
arch/arm/boot/dts/am43xx-clocks.dtsi +9 −0 Original line number Diff line number Diff line Loading @@ -486,6 +486,15 @@ reg = <0x4238>; }; dpll_clksel_mac_clk: dpll_clksel_mac_clk { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5_ck>; reg = <0x4234>; ti,bit-shift = <2>; ti,dividers = <2>, <5>; }; clk_32k_mosc_ck: clk_32k_mosc_ck { #clock-cells = <0>; compatible = "fixed-clock"; Loading
drivers/clk/ti/clk-43xx.c +1 −0 Original line number Diff line number Diff line Loading @@ -71,6 +71,7 @@ static struct ti_dt_clk am43xx_clks[] = { DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"), DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), Loading