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Commit a86b5505 authored by Shannon Zhao's avatar Shannon Zhao Committed by Marc Zyngier
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arm64: KVM: Add access handler for PMCEID0 and PMCEID1 register 



Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
UNDEFINED.

Signed-off-by: default avatarShannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 3965c3ce

arch/arm64/kvm/sys_regs.c

+24 −4
Original line number Diff line number Diff line
@@ -493,6 +493,26 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	return true;

}



static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,

			  const struct sys_reg_desc *r)

{

	u64 pmceid;



	if (!kvm_arm_pmu_v3_ready(vcpu))

		return trap_raz_wi(vcpu, p, r);



	BUG_ON(p->is_write);



	if (!(p->Op2 & 1))

		asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));

	else

		asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));



	p->regval = pmceid;



	return true;

}



/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */

#define DBG_BCR_BVR_WCR_WVR_EL1(n)					\

	/* DBGBVRn_EL1 */						\
@@ -695,10 +715,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	  access_pmselr, reset_unknown, PMSELR_EL0 },

	/* PMCEID0_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),

	  trap_raz_wi },

	  access_pmceid },

	/* PMCEID1_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),

	  trap_raz_wi },

	  access_pmceid },

	/* PMCCNTR_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),

	  trap_raz_wi },
@@ -944,8 +964,8 @@ static const struct sys_reg_desc cp15_regs[] = { 
	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },

	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },