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Commit 3965c3ce authored by Shannon Zhao's avatar Shannon Zhao Committed by Marc Zyngier
Browse files

arm64: KVM: Add access handler for PMSELR register 



Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.

Signed-off-by: default avatarShannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: default avatarAndrew Jones <drjones@redhat.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent ab946834

arch/arm64/include/asm/kvm_host.h

+1 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ enum vcpu_sysreg { 


	/* Performance Monitors Registers */

	PMCR_EL0,	/* Control Register */

	PMSELR_EL0,	/* Event Counter Selection Register */



	/* 32bit specific registers. Keep them at the end of the range */

	DACR32_EL2,	/* Domain Access Control Register */

arch/arm64/kvm/sys_regs.c

+18 −2
Original line number Diff line number Diff line
@@ -477,6 +477,22 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	return true;

}



static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,

			  const struct sys_reg_desc *r)

{

	if (!kvm_arm_pmu_v3_ready(vcpu))

		return trap_raz_wi(vcpu, p, r);



	if (p->is_write)

		vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;

	else

		/* return PMSELR.SEL field */

		p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)

			    & ARMV8_PMU_COUNTER_MASK;



	return true;

}



/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */

#define DBG_BCR_BVR_WCR_WVR_EL1(n)					\

	/* DBGBVRn_EL1 */						\
@@ -676,7 +692,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	  trap_raz_wi },

	/* PMSELR_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),

	  trap_raz_wi },

	  access_pmselr, reset_unknown, PMSELR_EL0 },

	/* PMCEID0_EL0 */

	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),

	  trap_raz_wi },
@@ -927,7 +943,7 @@ static const struct sys_reg_desc cp15_regs[] = { 
	{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },

	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },