Commit 9e290a19 authored May 12, 2009 by David Daney Committed by Ralf Baechle Jun 17, 2009

MIPS: Remove execution hazard barriers for Octeon.



The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 41f0e4d0

arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -47,6 +47,7 @@
		#define cpu_has_mips32r2 0
		#define cpu_has_mips64r1 0
		#define cpu_has_mips64r2 1
		#define cpu_has_mips_r2_exec_hazard 0
		#define cpu_has_dsp 0
		#define cpu_has_mipsmt 0
		#define cpu_has_userlocal 0