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Commit 41f0e4d0 authored by David Daney's avatar David Daney Committed by Ralf Baechle
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MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions. 



Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 95affdda

arch/mips/include/asm/cpu-features.h

+4 −0
Original line number Diff line number Diff line
@@ -147,6 +147,10 @@ 
#define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \

			 cpu_has_mips64r1 | cpu_has_mips64r2)



#ifndef cpu_has_mips_r2_exec_hazard

#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2

#endif



/*

 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other

 * pre-MIPS32/MIPS53 processors have CLO, CLZ.  For 64-bit kernels

arch/mips/mm/tlbex.c

+2 −1
Original line number Diff line number Diff line
@@ -259,6 +259,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, 
	}



	if (cpu_has_mips_r2) {

		if (cpu_has_mips_r2_exec_hazard)

			uasm_i_ehb(p);

		tlbw(p);

		return;