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Commit 9b13a93d authored by Borislav Petkov's avatar Borislav Petkov Committed by H. Peter Anvin
Browse files

x86, cpufeature: Convert more "features" to bugs 



X86_FEATURE_FXSAVE_LEAK, X86_FEATURE_11AP and
X86_FEATURE_CLFLUSH_MONITOR are not really features but synthetic bits
we use for applying different bug workarounds. Call them what they
really are, and make sure they get the proper cross-CPU behavior (OR
rather than AND).

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/1403042783-23278-1-git-send-email-bp@alien8.de


Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 03ab3da3

arch/x86/include/asm/apic.h

+1 −1
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ static inline void native_apic_mem_write(u32 reg, u32 v) 
{

	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);



	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,

	alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,

		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),

		       ASM_OUTPUT2("0" (v), "m" (*addr)));

}

arch/x86/include/asm/cpufeature.h

+17 −14
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ 
#define X86_FEATURE_P4		( 3*32+ 7) /* "" P4 */

#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */

#define X86_FEATURE_UP		( 3*32+ 9) /* smp kernel running on up */

#define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */

/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */

#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */

#define X86_FEATURE_PEBS	( 3*32+12) /* Precise-Event Based Sampling */

#define X86_FEATURE_BTS		( 3*32+13) /* Branch Trace Store */
@@ -90,13 +90,13 @@ 
#define X86_FEATURE_REP_GOOD	( 3*32+16) /* rep microcode works well */

#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */

#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */

#define X86_FEATURE_11AP	( 3*32+19) /* "" Bad local APIC aka 11AP */

/* free, was #define X86_FEATURE_11AP	( 3*32+19) * "" Bad local APIC aka 11AP */

#define X86_FEATURE_NOPL	( 3*32+20) /* The NOPL (0F 1F) instructions */

#define X86_FEATURE_ALWAYS	( 3*32+21) /* "" Always-present feature */

#define X86_FEATURE_XTOPOLOGY	( 3*32+22) /* cpu topology enum extensions */

#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */

#define X86_FEATURE_NONSTOP_TSC	( 3*32+24) /* TSC does not stop in C states */

#define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) /* "" clflush reqd with monitor */

/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */

#define X86_FEATURE_EXTD_APICID	( 3*32+26) /* has extended APICID (8 bits) */

#define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */

#define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */
@@ -241,6 +241,9 @@ 
#define X86_BUG_COMA		X86_BUG(2) /* Cyrix 6x86 coma */

#define X86_BUG_AMD_TLB_MMATCH	X86_BUG(3) /* AMD Erratum 383 */

#define X86_BUG_AMD_APIC_C1E	X86_BUG(4) /* AMD Erratum 400 */

#define X86_BUG_11AP		X86_BUG(5) /* Bad local APIC aka 11AP */

#define X86_BUG_FXSAVE_LEAK	X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */

#define X86_BUG_CLFLUSH_MONITOR	X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */



#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
@@ -547,9 +550,10 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit) 


#define cpu_has_bug(c, bit)		cpu_has(c, (bit))

#define set_cpu_bug(c, bit)		set_cpu_cap(c, (bit))

#define clear_cpu_bug(c, bit)	clear_cpu_cap(c, (bit));

#define clear_cpu_bug(c, bit)		clear_cpu_cap(c, (bit))



#define static_cpu_has_bug(bit)		static_cpu_has((bit))

#define static_cpu_has_bug_safe(bit)	static_cpu_has_safe((bit))

#define boot_cpu_has_bug(bit)		cpu_has_bug(&boot_cpu_data, (bit))



#define MAX_CPU_FEATURES		(NCAPINTS * 32)
@@ -560,5 +564,4 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit) 
					boot_cpu_data.x86_model



#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */



#endif /* _ASM_X86_CPUFEATURE_H */

arch/x86/include/asm/fpu-internal.h

+1 −1
Original line number Diff line number Diff line
@@ -293,7 +293,7 @@ static inline int restore_fpu_checking(struct task_struct *tsk) 
	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception

	   is pending.  Clear the x87 state here by setting it to fixed

	   values. "m" is a random variable that should be in L1 */

	if (unlikely(static_cpu_has_safe(X86_FEATURE_FXSAVE_LEAK))) {

	if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) {

		asm volatile(

			"fnclex\n\t"

			"emms\n\t"

arch/x86/include/asm/mwait.h

+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ static inline void __mwait(unsigned long eax, unsigned long ecx) 
static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)

{

	if (!current_set_polling_and_test()) {

		if (static_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) {

		if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {

			mb();

			clflush((void *)&current_thread_info()->flags);

			mb();

arch/x86/kernel/cpu/amd.c

+1 −1
Original line number Diff line number Diff line
@@ -595,7 +595,7 @@ static void init_amd(struct cpuinfo_x86 *c) 


	/* Enable workaround for FXSAVE leak */

	if (c->x86 >= 6)

		set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);

		set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);



	if (!c->x86_model_id[0]) {

		switch (c->x86) {