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Commit 9b01435d authored Jul 14, 2015 by Arun Siluvery Committed by Daniel Vetter Jul 15, 2015

drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken



In Indirect context w/a batch buffer,
+WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

v2: SKL revision id was used for BXT, copy paste error found during
internal review (Bob Beckett).

v3: explain why part of the WA is in Per ctx batch (Mika)

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent a4106a78

drivers/gpu/drm/i915/intel_lrc.c

+10 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1292,6 +1292,16 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
	struct drm_device *dev = ring->dev;		struct drm_device *dev = ring->dev;
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);		uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

			/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
			if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) \|\|
			(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
			wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
			wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
			wa_ctx_emit(batch, index,
			_MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
			wa_ctx_emit(batch, index, MI_NOOP);
			}

	/* WaDisableCtxRestoreArbitration:skl,bxt */		/* WaDisableCtxRestoreArbitration:skl,bxt */
	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) \|\|		if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) \|\|
	(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))		(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))

drivers/gpu/drm/i915/intel_ringbuffer.c

+5 −2

Original line number	Original line	Diff line number	Diff line
	@@ -946,8 +946,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
	WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
	GEN9_RHWO_OPTIMIZATION_DISABLE);		GEN9_RHWO_OPTIMIZATION_DISABLE);
	WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,		/*
	DISABLE_PIXEL_MASK_CAMMING);		* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
			* but we do that in per ctx batchbuffer as there is an issue
			* with this register not getting restored on ctx restore
			*/
	}		}

	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) \|\|		if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) \|\|