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Commit a4106a78 authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
Browse files

drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround 



In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt

v2: address static checker warning where unsigned value was checked for
less than zero which is never true (Dan Carpenter).

v3: The WA uses default value of GEN8_L3SQCREG4 during flush but that disables
some other WA; update default value to retain it and document dependency (Mika).

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0907c8f7

drivers/gpu/drm/i915/intel_lrc.c

+16 −0
Original line number Diff line number Diff line
@@ -1097,6 +1097,15 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring, 
{

	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);



	/*

	 * WaDisableLSQCROPERFforOCL:skl

	 * This WA is implemented in skl_init_clock_gating() but since

	 * this batch updates GEN8_L3SQCREG4 with default value we need to

	 * set this bit here to retain the WA during flush.

	 */

	if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)

		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;



	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8(1) |

				   MI_SRM_LRM_GLOBAL_GTT));

	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
@@ -1253,6 +1262,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, 
				    uint32_t *const batch,

				    uint32_t *offset)

{

	int ret;

	struct drm_device *dev = ring->dev;

	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
@@ -1261,6 +1271,12 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, 
	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))

		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);



	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */

	ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);

	if (ret < 0)

		return ret;

	index = ret;



	/* Pad to end of cacheline */

	while (index % CACHELINE_DWORDS)

		wa_ctx_emit(batch, index, MI_NOOP);

drivers/gpu/drm/i915/intel_pm.c

+3 −0
Original line number Diff line number Diff line
@@ -95,6 +95,9 @@ static void skl_init_clock_gating(struct drm_device *dev) 
			   _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));

	}



	/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes

	 * involving this register should also be added to WA batch as required.

	 */

	if (INTEL_REVID(dev) <= SKL_REVID_E0)

		/* WaDisableLSQCROPERFforOCL:skl */

		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |