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Commit 95ff439a authored by Russ Anderson's avatar Russ Anderson Committed by Tony Luck
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[IA64-SGI] Add new MMR definitions/Modify BTE initialiation&copy. 



patch 1:
	Add new MMR definitions.
	Modify BTE initialiation.
	Modify BTE copy.

Signed-off-by: default avatarRuss Anderson <rja@sgi.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent 4628d7ca

arch/ia64/sn/kernel/bte.c

+11 −9
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (c) 2000-2003 Silicon Graphics, Inc.  All Rights Reserved.

 * Copyright (c) 2000-2005 Silicon Graphics, Inc.  All Rights Reserved.

 */



#include <linux/config.h>
@@ -170,10 +170,6 @@ bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) 
	/* Initialize the notification to a known value. */

	*bte->most_rcnt_na = BTE_WORD_BUSY;



	/* Set the status reg busy bit and transfer length */

	BTE_PRINTKV(("IBLS = 0x%lx\n", IBLS_BUSY | transfer_size));

	BTE_LNSTAT_STORE(bte, IBLS_BUSY | transfer_size);



	/* Set the source and destination registers */

	BTE_PRINTKV(("IBSA = 0x%lx)\n", (TO_PHYS(src))));

	BTE_SRC_STORE(bte, TO_PHYS(src));
@@ -188,7 +184,7 @@ bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) 


	/* Initiate the transfer */

	BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode)));

	BTE_CTRL_STORE(bte, BTE_VALID_MODE(mode));

	BTE_START_TRANSFER(bte, transfer_size, BTE_VALID_MODE(mode));



	itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec);
@@ -429,10 +425,16 @@ void bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode) 
	mynodepda->bte_recovery_timer.data = (unsigned long)mynodepda;



	for (i = 0; i < BTES_PER_NODE; i++) {

		u64 *base_addr;



		/* Which link status register should we use? */

		unsigned long link_status = (i == 0 ? IIO_IBLS0 : IIO_IBLS1);

		mynodepda->bte_if[i].bte_base_addr = (u64 *)

		    REMOTE_HUB_ADDR(cnodeid_to_nasid(cnode), link_status);

		base_addr = (u64 *)

		    REMOTE_HUB_ADDR(cnodeid_to_nasid(cnode), BTE_BASE_ADDR(i));

		mynodepda->bte_if[i].bte_base_addr = base_addr;

		mynodepda->bte_if[i].bte_source_addr = BTE_SOURCE_ADDR(base_addr);

		mynodepda->bte_if[i].bte_destination_addr = BTE_DEST_ADDR(base_addr);

		mynodepda->bte_if[i].bte_control_addr = BTE_CTRL_ADDR(base_addr);

		mynodepda->bte_if[i].bte_notify_addr = BTE_NOTIF_ADDR(base_addr);



		/*

		 * Initialize the notification and spinlock

include/asm-ia64/sn/bte.h

+47 −6
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (c) 2000-2004 Silicon Graphics, Inc.  All Rights Reserved.

 * Copyright (c) 2000-2005 Silicon Graphics, Inc.  All Rights Reserved.

 */
@@ -13,8 +13,12 @@ 
#include <linux/timer.h>

#include <linux/spinlock.h>

#include <linux/cache.h>

#include <asm/sn/pda.h>

#include <asm/sn/types.h>

#include <asm/sn/shub_mmr.h>



#define IBCT_NOTIFY             (0x1UL << 4)

#define IBCT_ZFIL_MODE          (0x1UL << 0)



/* #define BTE_DEBUG */

/* #define BTE_DEBUG_VERBOSE */
@@ -39,8 +43,36 @@ 




/* Define hardware */

#define BTES_PER_NODE 2

#define BTES_PER_NODE (is_shub2() ? 4 : 2)

#define MAX_BTES_PER_NODE 4



#define BTE2OFF_CTRL	(0)

#define BTE2OFF_SRC	(SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)

#define BTE2OFF_DEST	(SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)

#define BTE2OFF_NOTIFY	(SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)



#define BTE_BASE_ADDR(interface) 				\

    (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 :		\

		  (interface == 1) ? SH2_BT_ENG_CSR_1 :		\

		  (interface == 2) ? SH2_BT_ENG_CSR_2 :		\

		  		     SH2_BT_ENG_CSR_3 		\

		: (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)



#define BTE_SOURCE_ADDR(base)					\

    (is_shub2() ? base + (BTE2OFF_SRC/8) 			\

		: base + (BTEOFF_SRC/8))



#define BTE_DEST_ADDR(base)					\

    (is_shub2() ? base + (BTE2OFF_DEST/8) 			\

		: base + (BTEOFF_DEST/8))



#define BTE_CTRL_ADDR(base)					\

    (is_shub2() ? base + (BTE2OFF_CTRL/8) 			\

		: base + (BTEOFF_CTRL/8))



#define BTE_NOTIF_ADDR(base)					\

    (is_shub2() ? base + (BTE2OFF_NOTIFY/8) 			\

		: base + (BTEOFF_NOTIFY/8))



/* Define hardware modes */

#define BTE_NOTIFY (IBCT_NOTIFY)
@@ -68,14 +100,18 @@ 
#define BTE_LNSTAT_STORE(_bte, _x)					\

			HUB_S(_bte->bte_base_addr, (_x))

#define BTE_SRC_STORE(_bte, _x)						\

			HUB_S(_bte->bte_base_addr + (BTEOFF_SRC/8), (_x))

			HUB_S(_bte->bte_source_addr, (_x))

#define BTE_DEST_STORE(_bte, _x)					\

			HUB_S(_bte->bte_base_addr + (BTEOFF_DEST/8), (_x))

			HUB_S(_bte->bte_destination_addr, (_x))

#define BTE_CTRL_STORE(_bte, _x)					\

			HUB_S(_bte->bte_base_addr + (BTEOFF_CTRL/8), (_x))

			HUB_S(_bte->bte_control_addr, (_x))

#define BTE_NOTIF_STORE(_bte, _x)					\

			HUB_S(_bte->bte_base_addr + (BTEOFF_NOTIFY/8), (_x))

			HUB_S(_bte->bte_notify_addr, (_x))



#define BTE_START_TRANSFER(_bte, _len, _mode)				\

	is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \

		: BTE_LNSTAT_STORE(_bte, _len);				\

		  BTE_CTRL_STORE(_bte, _mode)



/* Possible results from bte_copy and bte_unaligned_copy */

/* The following error codes map into the BTE hardware codes
@@ -110,6 +146,10 @@ typedef enum { 
struct bteinfo_s {

	volatile u64 notify ____cacheline_aligned;

	u64 *bte_base_addr ____cacheline_aligned;

	u64 *bte_source_addr;

	u64 *bte_destination_addr;

	u64 *bte_control_addr;

	u64 *bte_notify_addr;

	spinlock_t spinlock;

	cnodeid_t bte_cnode;	/* cnode                            */

	int bte_error_count;	/* Number of errors encountered     */
@@ -117,6 +157,7 @@ struct bteinfo_s { 
	int cleanup_active;	/* Interface is locked for cleanup  */

	volatile bte_result_t bh_error;	/* error while processing   */

	volatile u64 *most_rcnt_na;

	struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];

};

include/asm-ia64/sn/nodepda.h

+2 −2
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.

 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.

 */

#ifndef _ASM_IA64_SN_NODEPDA_H

#define _ASM_IA64_SN_NODEPDA_H
@@ -43,7 +43,7 @@ struct nodepda_s { 
	/*

	 * The BTEs on this node are shared by the local cpus

	 */

	struct bteinfo_s	bte_if[BTES_PER_NODE];	/* Virtual Interface */

	struct bteinfo_s	bte_if[MAX_BTES_PER_NODE];	/* Virtual Interface */

	struct timer_list	bte_recovery_timer;

	spinlock_t		bte_recovery_lock;

include/asm-ia64/sn/pda.h

+1 −2
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.

 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.

 */

#ifndef _ASM_IA64_SN_PDA_H

#define _ASM_IA64_SN_PDA_H
@@ -11,7 +11,6 @@ 
#include <linux/cache.h>

#include <asm/percpu.h>

#include <asm/system.h>

#include <asm/sn/bte.h>





/*

include/asm-ia64/sn/shub_mmr.h

+19 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.

 * Copyright (c) 2001-2005 Silicon Graphics, Inc.  All rights reserved.

 */



#ifndef _ASM_IA64_SN_SHUB_MMR_H
@@ -455,4 +455,22 @@ 
#define SH_INT_CMPC		shubmmr(SH, INT_CMPC)

#define SH_INT_CMPD		shubmmr(SH, INT_CMPD)



/* ========================================================================== */

/*                        Register "SH2_BT_ENG_CSR_0"                         */

/*                    Engine 0 Control and Status Register                    */

/* ========================================================================== */



#define SH2_BT_ENG_CSR_0                         0x0000000030040000

#define SH2_BT_ENG_SRC_ADDR_0                    0x0000000030040080

#define SH2_BT_ENG_DEST_ADDR_0                   0x0000000030040100

#define SH2_BT_ENG_NOTIF_ADDR_0                  0x0000000030040180



/* ========================================================================== */

/*                       BTE interfaces 1-3                                   */

/* ========================================================================== */



#define SH2_BT_ENG_CSR_1                         0x0000000030050000

#define SH2_BT_ENG_CSR_2                         0x0000000030060000

#define SH2_BT_ENG_CSR_3                         0x0000000030070000



#endif /* _ASM_IA64_SN_SHUB_MMR_H */