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Commit 88f18476 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'samsung-dt-devfreq-4.7' of... 

Merge tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late

Merge "ARM: dts: exynos: Devfreq for v4.7: from Krzysztof Kozłowski:

Topic branch for Device Tree changes adding new generic devfreq driver, for
v4.7:
1. Add bus nodes for Exynos3250, Exynos4x12, Exynos4210 and Exynos542x.
2. Split out common PPMU (Performance Monitoring Unit) nodes into separate
   DTSI. The PPMU provides performance data for devfreq.
3. Add NoCP (Network on Chip Probe) node for Exynos542x. On this SoC, like PPMU
   on older designs, provides performance data for devfreq.
4. Enable DFVS (Dynamic Voltage and Frequency Scaling) on boards:
   - Exynos3250 Rinato,
   - Exynos4412 Odroid-X/X2/U3 and Trats2,
   - Exynos5422 Odroid XU3/XU3-Lite/XU4.

* tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3
  ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC
  ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC
  ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3
  ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
  ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato
  ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes
  ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210
  ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12
  ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12
  ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250
  ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk
  ARM: dts: exynos: Add DMC bus node for Exynos3250
  clk: samsung: exynos542x: Add the clock id for ACLK
  dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
parents 28f31369 3f2129fd

arch/arm/boot/dts/exynos3250-monk.dts

+7 −40
Original line number Original line Diff line number Diff line
@@ -14,6 +14,7 @@ 




/dts-v1/;

/dts-v1/;

#include "exynos3250.dtsi"

#include "exynos3250.dtsi"

#include "exynos4412-ppmu-common.dtsi"

#include <dt-bindings/input/input.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/clock/samsung,s2mps11.h>

#include <dt-bindings/clock/samsung,s2mps11.h>
@@ -156,6 +157,12 @@ 
	};

	};

};

};





&bus_dmc {

	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;

	vdd-supply = <&buck1_reg>;

	status = "okay";

};



&cpu0 {

&cpu0 {

	cpu0-supply = <&buck2_reg>;

	cpu0-supply = <&buck2_reg>;

};

};
@@ -458,46 +465,6 @@ 
	status = "okay";

	status = "okay";

};

};





&ppmu_dmc0 {

	status = "okay";



	events {

		ppmu_dmc0_3: ppmu-event3-dmc0 {

			event-name = "ppmu-event3-dmc0";

		};

	};

};



&ppmu_dmc1 {

	status = "okay";



	events {

		ppmu_dmc1_3: ppmu-event3-dmc1 {

			event-name = "ppmu-event3-dmc1";

		};

	};

};



&ppmu_leftbus {

	status = "okay";



	events {

		ppmu_leftbus_3: ppmu-event3-leftbus {

			event-name = "ppmu-event3-leftbus";

		};

	};

};



&ppmu_rightbus {

	status = "okay";



	events {

		ppmu_rightbus_3: ppmu-event3-rightbus {

			event-name = "ppmu-event3-rightbus";

		};

	};

};



&xusbxti {

&xusbxti {

	clock-frequency = <24000000>;

	clock-frequency = <24000000>;

};

};

arch/arm/boot/dts/exynos3250-rinato.dts

+48 −40
Original line number Original line Diff line number Diff line
@@ -14,6 +14,7 @@ 




/dts-v1/;

/dts-v1/;

#include "exynos3250.dtsi"

#include "exynos3250.dtsi"

#include "exynos4412-ppmu-common.dtsi"

#include <dt-bindings/input/input.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/clock/samsung,s2mps11.h>

#include <dt-bindings/clock/samsung,s2mps11.h>
@@ -147,6 +148,53 @@ 
	};

	};

};

};





&bus_dmc {

	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;

	vdd-supply = <&buck1_reg>;

	status = "okay";

};



&bus_leftbus {

	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;

	vdd-supply = <&buck3_reg>;

	status = "okay";

};



&bus_rightbus {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_lcd0 {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_fsys {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_mcuisp {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_isp {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_peril {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_mfc {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&cpu0 {

&cpu0 {

	cpu0-supply = <&buck2_reg>;

	cpu0-supply = <&buck2_reg>;

};

};
@@ -635,46 +683,6 @@ 
	status = "okay";

	status = "okay";

};

};





&ppmu_dmc0 {

	status = "okay";



	events {

		ppmu_dmc0_3: ppmu-event3-dmc0 {

			event-name = "ppmu-event3-dmc0";

		};

	};

};



&ppmu_dmc1 {

	status = "okay";



	events {

		ppmu_dmc1_3: ppmu-event3-dmc1 {

			event-name = "ppmu-event3-dmc1";

		};

	};

};



&ppmu_leftbus {

	status = "okay";



	events {

		ppmu_leftbus_3: ppmu-event3-leftbus {

			event-name = "ppmu-event3-leftbus";

		};

	};

};



&ppmu_rightbus {

	status = "okay";



	events {

		ppmu_rightbus_3: ppmu-event3-rightbus {

			event-name = "ppmu-event3-rightbus";

		};

	};

};



&xusbxti {

&xusbxti {

	clock-frequency = <24000000>;

	clock-frequency = <24000000>;

};

};

arch/arm/boot/dts/exynos3250.dtsi

+181 −0
Original line number Original line Diff line number Diff line
@@ -688,6 +688,187 @@ 
			clock-names = "ppmu";

			clock-names = "ppmu";

			status = "disabled";

			status = "disabled";

		};

		};



		bus_dmc: bus_dmc {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu_dmc CLK_DIV_DMC>;

			clock-names = "bus";

			operating-points-v2 = <&bus_dmc_opp_table>;

			status = "disabled";

		};



		bus_dmc_opp_table: opp_table1 {

			compatible = "operating-points-v2";

			opp-shared;



			opp@50000000 {

				opp-hz = /bits/ 64 <50000000>;

				opp-microvolt = <800000>;

			};

			opp@100000000 {

				opp-hz = /bits/ 64 <100000000>;

				opp-microvolt = <800000>;

			};

			opp@134000000 {

				opp-hz = /bits/ 64 <134000000>;

				opp-microvolt = <800000>;

			};

			opp@200000000 {

				opp-hz = /bits/ 64 <200000000>;

				opp-microvolt = <825000>;

			};

			opp@400000000 {

				opp-hz = /bits/ 64 <400000000>;

				opp-microvolt = <875000>;

			};

		};



		bus_leftbus: bus_leftbus {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu CLK_DIV_GDL>;

			clock-names = "bus";

			operating-points-v2 = <&bus_leftbus_opp_table>;

			status = "disabled";

		};



		bus_rightbus: bus_rightbus {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu CLK_DIV_GDR>;

			clock-names = "bus";

			operating-points-v2 = <&bus_leftbus_opp_table>;

			status = "disabled";

		};



		bus_lcd0: bus_lcd0 {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu CLK_DIV_ACLK_160>;

			clock-names = "bus";

			operating-points-v2 = <&bus_leftbus_opp_table>;

			status = "disabled";

		};



		bus_fsys: bus_fsys {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu CLK_DIV_ACLK_200>;

			clock-names = "bus";

			operating-points-v2 = <&bus_leftbus_opp_table>;

			status = "disabled";

		};



		bus_mcuisp: bus_mcuisp {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;

			clock-names = "bus";

			operating-points-v2 = <&bus_mcuisp_opp_table>;

			status = "disabled";

		};



		bus_isp: bus_isp {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu CLK_DIV_ACLK_266>;

			clock-names = "bus";

			operating-points-v2 = <&bus_isp_opp_table>;

			status = "disabled";

		};



		bus_peril: bus_peril {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu CLK_DIV_ACLK_100>;

			clock-names = "bus";

			operating-points-v2 = <&bus_peril_opp_table>;

			status = "disabled";

		};



		bus_mfc: bus_mfc {

			compatible = "samsung,exynos-bus";

			clocks = <&cmu CLK_SCLK_MFC>;

			clock-names = "bus";

			operating-points-v2 = <&bus_leftbus_opp_table>;

			status = "disabled";

		};



		bus_leftbus_opp_table: opp_table2 {

			compatible = "operating-points-v2";

			opp-shared;



			opp@50000000 {

				opp-hz = /bits/ 64 <50000000>;

				opp-microvolt = <900000>;

			};

			opp@80000000 {

				opp-hz = /bits/ 64 <80000000>;

				opp-microvolt = <900000>;

			};

			opp@100000000 {

				opp-hz = /bits/ 64 <100000000>;

				opp-microvolt = <1000000>;

			};

			opp@134000000 {

				opp-hz = /bits/ 64 <134000000>;

				opp-microvolt = <1000000>;

			};

			opp@200000000 {

				opp-hz = /bits/ 64 <200000000>;

				opp-microvolt = <1000000>;

			};

		};



		bus_mcuisp_opp_table: opp_table3 {

			compatible = "operating-points-v2";

			opp-shared;



			opp@50000000 {

				opp-hz = /bits/ 64 <50000000>;

			};

			opp@80000000 {

				opp-hz = /bits/ 64 <80000000>;

			};

			opp@100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

			opp@200000000 {

				opp-hz = /bits/ 64 <200000000>;

			};

			opp@400000000 {

				opp-hz = /bits/ 64 <400000000>;

			};

		};



		bus_isp_opp_table: opp_table4 {

			compatible = "operating-points-v2";

			opp-shared;



			opp@50000000 {

				opp-hz = /bits/ 64 <50000000>;

			};

			opp@80000000 {

				opp-hz = /bits/ 64 <80000000>;

			};

			opp@100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

			opp@200000000 {

				opp-hz = /bits/ 64 <200000000>;

			};

			opp@300000000 {

				opp-hz = /bits/ 64 <300000000>;

			};

		};



		bus_peril_opp_table: opp_table5 {

			compatible = "operating-points-v2";

			opp-shared;



			opp@50000000 {

				opp-hz = /bits/ 64 <50000000>;

			};

			opp@80000000 {

				opp-hz = /bits/ 64 <80000000>;

			};

			opp@100000000 {

				opp-hz = /bits/ 64 <100000000>;

			};

		};

	};

	};

};

};

arch/arm/boot/dts/exynos4210.dtsi

+159 −0
Original line number Original line Diff line number Diff line
@@ -257,6 +257,165 @@ 
		power-domains = <&pd_lcd1>;

		power-domains = <&pd_lcd1>;

		#iommu-cells = <0>;

		#iommu-cells = <0>;

	};

	};



	bus_dmc: bus_dmc {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_DMC>;

		clock-names = "bus";

		operating-points-v2 = <&bus_dmc_opp_table>;

		status = "disabled";

	};



	bus_acp: bus_acp {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_ACP>;

		clock-names = "bus";

		operating-points-v2 = <&bus_acp_opp_table>;

		status = "disabled";

	};



	bus_peri: bus_peri {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_ACLK100>;

		clock-names = "bus";

		operating-points-v2 = <&bus_peri_opp_table>;

		status = "disabled";

	};



	bus_fsys: bus_fsys {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_ACLK133>;

		clock-names = "bus";

		operating-points-v2 = <&bus_fsys_opp_table>;

		status = "disabled";

	};



	bus_display: bus_display {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_ACLK160>;

		clock-names = "bus";

		operating-points-v2 = <&bus_display_opp_table>;

		status = "disabled";

	};



	bus_lcd0: bus_lcd0 {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_ACLK200>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_leftbus: bus_leftbus {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_GDL>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_rightbus: bus_rightbus {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_DIV_GDR>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_mfc: bus_mfc {

		compatible = "samsung,exynos-bus";

		clocks = <&clock CLK_SCLK_MFC>;

		clock-names = "bus";

		operating-points-v2 = <&bus_leftbus_opp_table>;

		status = "disabled";

	};



	bus_dmc_opp_table: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@134000000 {

			opp-hz = /bits/ 64 <134000000>;

			opp-microvolt = <1025000>;

		};

		opp@267000000 {

			opp-hz = /bits/ 64 <267000000>;

			opp-microvolt = <1050000>;

		};

		opp@400000000 {

			opp-hz = /bits/ 64 <400000000>;

			opp-microvolt = <1150000>;

		};

	};



	bus_acp_opp_table: opp_table2 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@134000000 {

			opp-hz = /bits/ 64 <134000000>;

		};

		opp@160000000 {

			opp-hz = /bits/ 64 <160000000>;

		};

		opp@200000000 {

			opp-hz = /bits/ 64 <200000000>;

		};

	};



	bus_peri_opp_table: opp_table3 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@5000000 {

			opp-hz = /bits/ 64 <5000000>;

		};

		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

		};

	};



	bus_fsys_opp_table: opp_table4 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@10000000 {

			opp-hz = /bits/ 64 <10000000>;

		};

		opp@134000000 {

			opp-hz = /bits/ 64 <134000000>;

		};

	};



	bus_display_opp_table: opp_table5 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

		};

		opp@134000000 {

			opp-hz = /bits/ 64 <134000000>;

		};

		opp@160000000 {

			opp-hz = /bits/ 64 <160000000>;

		};

	};



	bus_leftbus_opp_table: opp_table6 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

		};

		opp@160000000 {

			opp-hz = /bits/ 64 <160000000>;

		};

		opp@200000000 {

			opp-hz = /bits/ 64 <200000000>;

		};

	};

};

};





&gic {

&gic {

arch/arm/boot/dts/exynos4412-odroid-common.dtsi

+52 −4
Original line number Original line Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <dt-bindings/input/input.h>

#include <dt-bindings/input/input.h>

#include <dt-bindings/clock/maxim,max77686.h>

#include <dt-bindings/clock/maxim,max77686.h>

#include "exynos4412.dtsi"

#include "exynos4412.dtsi"

#include "exynos4412-ppmu-common.dtsi"

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/gpio/gpio.h>





/ {

/ {
@@ -108,6 +109,53 @@ 
	};

	};

};

};





&bus_dmc {

	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;

	vdd-supply = <&buck1_reg>;

	status = "okay";

};



&bus_acp {

	devfreq = <&bus_dmc>;

	status = "okay";

};



&bus_c2c {

	devfreq = <&bus_dmc>;

	status = "okay";

};



&bus_leftbus {

	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;

	vdd-supply = <&buck3_reg>;

	status = "okay";

};



&bus_rightbus {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_display {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_fsys {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_peri {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&bus_mfc {

	devfreq = <&bus_leftbus>;

	status = "okay";

};



&cpu0 {

&cpu0 {

	cpu0-supply = <&buck2_reg>;

	cpu0-supply = <&buck2_reg>;

};

};
@@ -355,8 +403,8 @@ 




			buck1_reg: BUCK1 {

			buck1_reg: BUCK1 {

				regulator-name = "vdd_mif";

				regulator-name = "vdd_mif";

				regulator-min-microvolt = <1000000>;

				regulator-min-microvolt = <900000>;

				regulator-max-microvolt = <1000000>;

				regulator-max-microvolt = <1100000>;

				regulator-always-on;

				regulator-always-on;

				regulator-boot-on;

				regulator-boot-on;

			};

			};
@@ -371,8 +419,8 @@ 




			buck3_reg: BUCK3 {

			buck3_reg: BUCK3 {

				regulator-name = "vdd_int";

				regulator-name = "vdd_int";

				regulator-min-microvolt = <1000000>;

				regulator-min-microvolt = <900000>;

				regulator-max-microvolt = <1000000>;

				regulator-max-microvolt = <1050000>;

				regulator-always-on;

				regulator-always-on;

				regulator-boot-on;

				regulator-boot-on;

			};

			};