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Commit 880d54ff authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Stephen Boyd
Browse files

drivers: clk: st: Simplify clock binding of STiH4xx platforms 

This patch reworks the clock binding to avoid too much detail in DT.
Now we have only compatible string per type of clock
(remark from Rob https://lkml.org/lkml/2016/5/25/492

)

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 7df404c9

Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ This binding uses the common clock binding[1]. 
Required properties:



- compatible : shall be:

	"st,stih407-clkgen-a9-mux",	"st,clkgen-mux"

	"st,stih407-clkgen-a9-mux"



- #clock-cells : from common clock binding; shall be set to 0.

Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt

+5 −6
Original line number Diff line number Diff line
@@ -9,11 +9,10 @@ Base address is located to the parent node. See clock binding[2] 
Required properties:



- compatible : shall be:

	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"

	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"

	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"

	"st,stih418-plls-c28-a9",	"st,clkgen-plls-c32"

	"st,clkgen-pll0"

	"st,clkgen-pll1"

	"st,stih407-clkgen-plla9"

	"st,stih418-clkgen-plla9"



- #clock-cells : From common clock binding; shall be set to 1.
@@ -29,7 +28,7 @@ Example: 


		clockgen_a9_pll: clockgen-a9-pll {

			#clock-cells = <1>;

			compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";

			compatible = "st,stih407-clkgen-plla9";



			clocks = <&clk_sysin>;

Documentation/devicetree/bindings/clock/st/st,clkgen.txt

+1 −1
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ Example: 


		clk_s_a0_pll: clk-s-a0-pll {

			#clock-cells = <1>;

			compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";

			compatible = "st,clkgen-pll0";



			clocks = <&clk_sysin>;

Documentation/devicetree/bindings/clock/st/st,quadfs.txt

+3 −3
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ This binding uses the common clock binding[1]. 


Required properties:

- compatible : shall be:

  "st,stih407-quadfs660-C",	"st,quadfs"

  "st,stih407-quadfs660-D",	"st,quadfs"

  "st,quadfs"

  "st,quadfs-pll"





- #clock-cells : from common clock binding; shall be set to 1.
@@ -33,7 +33,7 @@ Example: 


	clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {

		#clock-cells = <1>;

		compatible = "st,stih407-quadfs660-C", "st,quadfs";

		compatible = "st,quadfs-pll";

		reg = <0x9103000 0x1000>;



		clocks = <&clk_sysin>;

drivers/clk/st/clkgen-fsyn.c

+17 −24
Original line number Diff line number Diff line
@@ -819,18 +819,6 @@ static struct clk * __init st_clk_register_quadfs_fsynth( 
	return clk;

}



static const struct of_device_id quadfs_of_match[] = {

	{

		.compatible = "st,stih407-quadfs660-C",

		.data = &st_fs660c32_C

	},

	{

		.compatible = "st,stih407-quadfs660-D",

		.data = &st_fs660c32_D

	},

	{}

};



static void __init st_of_create_quadfs_fsynths(

		struct device_node *np, const char *pll_name,

		struct clkgen_quadfs_data *quadfs, void __iomem *reg,
@@ -890,18 +878,14 @@ static void __init st_of_create_quadfs_fsynths( 
	of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);

}



static void __init st_of_quadfs_setup(struct device_node *np)

static void __init st_of_quadfs_setup(struct device_node *np,

		struct clkgen_quadfs_data *data)

{

	const struct of_device_id *match;

	struct clk *clk;

	const char *pll_name, *clk_parent_name;

	void __iomem *reg;

	spinlock_t *lock;



	match = of_match_node(quadfs_of_match, np);

	if (WARN_ON(!match))

		return;



	reg = of_iomap(np, 0);

	if (!reg)

		return;
@@ -920,8 +904,8 @@ static void __init st_of_quadfs_setup(struct device_node *np) 


	spin_lock_init(lock);



	clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name,

			(struct clkgen_quadfs_data *) match->data, reg, lock);

	clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, data,

			reg, lock);

	if (IS_ERR(clk))

		goto err_exit;

	else
@@ -930,11 +914,20 @@ static void __init st_of_quadfs_setup(struct device_node *np) 
			__clk_get_name(clk_get_parent(clk)),

			(unsigned int)clk_get_rate(clk));



	st_of_create_quadfs_fsynths(np, pll_name,

				    (struct clkgen_quadfs_data *)match->data,

				    reg, lock);

	st_of_create_quadfs_fsynths(np, pll_name, data, reg, lock);



err_exit:

	kfree(pll_name); /* No longer need local copy of the PLL name */

}

CLK_OF_DECLARE(quadfs, "st,quadfs", st_of_quadfs_setup);
 


static void __init st_of_quadfs660C_setup(struct device_node *np)

{

	st_of_quadfs_setup(np, (struct clkgen_quadfs_data *) &st_fs660c32_C);

}

CLK_OF_DECLARE(quadfs660C, "st,quadfs-pll", st_of_quadfs660C_setup);



static void __init st_of_quadfs660D_setup(struct device_node *np)

{

	st_of_quadfs_setup(np, (struct clkgen_quadfs_data *) &st_fs660c32_D);

}

CLK_OF_DECLARE(quadfs660D, "st,quadfs", st_of_quadfs660D_setup);