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Commit 7df404c9 authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Stephen Boyd
Browse files

drivers: clk: st: Remove stih415-416 clock support 



STiH415 and STiH416 platforms are no longer used.
these platforms will be deprecated for the next kernel.

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent f5644f10

Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt

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+0 −49
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Binding for a ST divider and multiplexer clock driver.



This binding uses the common clock binding[1].

Base address is located to the parent node. See clock binding[2]



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt



Required properties:



- compatible : shall be:

	"st,clkgena-divmux-c65-hs",	"st,clkgena-divmux"

	"st,clkgena-divmux-c65-ls",	"st,clkgena-divmux"

	"st,clkgena-divmux-c32-odf0",	"st,clkgena-divmux"

	"st,clkgena-divmux-c32-odf1",	"st,clkgena-divmux"

	"st,clkgena-divmux-c32-odf2",	"st,clkgena-divmux"

	"st,clkgena-divmux-c32-odf3",	"st,clkgena-divmux"



- #clock-cells : From common clock binding; shall be set to 1.



- clocks : From common clock binding



- clock-output-names : From common clock binding.



Example:



	clockgen-a@fd345000 {

		reg = <0xfd345000 0xb50>;



		clk_m_a1_div1: clk-m-a1-div1 {

			#clock-cells = <1>;

			compatible = "st,clkgena-divmux-c32-odf1",

				     "st,clkgena-divmux";



			clocks = <&clk_m_a1_osc_prediv>,

				 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */

				 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */



			clock-output-names = "clk-m-rx-icn-ts",

					     "clk-m-rx-icn-vdp-0",

					     "", /* unused */

					     "clk-m-prv-t1-bus",

					     "clk-m-icn-reg-12",

					     "clk-m-icn-reg-10",

					     "", /* unused */

					     "clk-m-icn-st231";

		};

	};

Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt

+7 −11
Original line number Diff line number Diff line
@@ -10,13 +10,6 @@ This binding uses the common clock binding[1]. 
Required properties:



- compatible : shall be:

	"st,stih416-clkgenc-vcc-hd",	"st,clkgen-mux"

	"st,stih416-clkgenf-vcc-fvdp",	"st,clkgen-mux"

	"st,stih416-clkgenf-vcc-hva", 	"st,clkgen-mux"

	"st,stih416-clkgenf-vcc-hd",	"st,clkgen-mux"

	"st,stih416-clkgenf-vcc-sd",	"st,clkgen-mux"

	"st,stih415-clkgen-a9-mux",	"st,clkgen-mux"

	"st,stih416-clkgen-a9-mux",	"st,clkgen-mux"

	"st,stih407-clkgen-a9-mux",	"st,clkgen-mux"



- #clock-cells : from common clock binding; shall be set to 0.
@@ -27,10 +20,13 @@ Required properties: 


Example:



	clk_m_hva: clk-m-hva@fd690868 {

	clk_m_a9: clk-m-a9@92b0000 {

		#clock-cells = <0>;

		compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";

		reg = <0xfd690868 4>;

		compatible = "st,stih407-clkgen-a9-mux";

		reg = <0x92b0000 0x10000>;



		clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;

		clocks = <&clockgen_a9_pll 0>,

			 <&clockgen_a9_pll 0>,

			 <&clk_s_c0_flexgen 13>,

			 <&clk_m_a9_ext2f_div2>;

	};

Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt

+6 −20
Original line number Diff line number Diff line
@@ -9,25 +9,12 @@ Base address is located to the parent node. See clock binding[2] 
Required properties:



- compatible : shall be:

	"st,clkgena-prediv-c65",	"st,clkgena-prediv"

	"st,clkgena-prediv-c32",	"st,clkgena-prediv"



	"st,clkgena-plls-c65"

	"st,plls-c32-a1x-0",		"st,clkgen-plls-c32"

	"st,plls-c32-a1x-1",		"st,clkgen-plls-c32"

	"st,stih415-plls-c32-a9",	"st,clkgen-plls-c32"

	"st,stih415-plls-c32-ddr",	"st,clkgen-plls-c32"

	"st,stih416-plls-c32-a9",	"st,clkgen-plls-c32"

	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"

	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"

	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"

	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"

	"st,stih418-plls-c28-a9",	"st,clkgen-plls-c32"



	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"

	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"



- #clock-cells : From common clock binding; shall be set to 1.



- clocks : From common clock binding
@@ -36,17 +23,16 @@ Required properties: 


Example:



	clockgen-a@fee62000 {

		reg = <0xfee62000 0xb48>;

	clockgen-a9@92b0000 {

		compatible = "st,clkgen-c32";

		reg = <0x92b0000 0xffff>;



		clk_s_a0_pll: clk-s-a0-pll {

		clockgen_a9_pll: clockgen-a9-pll {

			#clock-cells = <1>;

			compatible = "st,clkgena-plls-c65";

			compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";



			clocks = <&clk_sysin>;



			clock-output-names = "clk-s-a0-pll0-hs",

					     "clk-s-a0-pll0-ls",

					     "clk-s-a0-pll1";

			clock-output-names = "clockgen-a9-pll-odf";

		};

	};

Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt

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Binding for a ST pre-divider clock driver.



This binding uses the common clock binding[1].

Base address is located to the parent node. See clock binding[2]



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt



Required properties:



- compatible : shall be:

	"st,clkgena-prediv-c65",	"st,clkgena-prediv"

	"st,clkgena-prediv-c32",	"st,clkgena-prediv"



- #clock-cells : From common clock binding; shall be set to 0.



- clocks : From common clock binding



- clock-output-names : From common clock binding.



Example:



	clockgen-a@fd345000 {

		reg = <0xfd345000 0xb50>;



		clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {

			#clock-cells = <0>;

			compatible = "st,clkgena-prediv-c32",

				     "st,clkgena-prediv";



			clocks = <&clk_sysin>;



			clock-output-names = "clk-m-a2-osc-prediv";

		};

	};

Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt

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Binding for a type of STMicroelectronics clock crossbar (VCC).



The crossbar can take up to 4 input clocks and control up to 16

output clocks. Not all inputs or outputs have to be in use in a

particular instantiation. Each output can be individually enabled,

select any of the input clocks and apply a divide (by 1,2,4 or 8) to

that selected clock.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:



- compatible : shall be:

	"st,stih416-clkgenc",		"st,vcc"

	"st,stih416-clkgenf",		"st,vcc"



- #clock-cells : from common clock binding; shall be set to 1.



- reg : A Base address and length of the register set.



- clocks : from common clock binding



- clock-output-names : From common clock binding. The block has 16

                       clock outputs but not all of them in a specific instance

                       have to be used in the SoC. If a clock name is left as

                       an empty string then no clock will be created for the

                       output associated with that string index. If fewer than

                       16 strings are provided then no clocks will be created

                       for the remaining outputs.



Example:



	clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {

		#clock-cells = <1>;

		compatible = "st,stih416-clkgenc", "st,clkgen-vcc";

		reg = <0xfe8308ac 12>;



		clocks = <&clk_s_vcc_hd>,

			 <&clockgen_c 1>,

			 <&clk_s_tmds_fromphy>,

			 <&clockgen_c 2>;



		clock-output-names  = "clk-s-pix-hdmi",

				      "clk-s-pix-dvo",

				      "clk-s-out-dvo",

				      "clk-s-pix-hd",

				      "clk-s-hddac",

				      "clk-s-denc",

				      "clk-s-sddac",

				      "clk-s-pix-main",

				      "clk-s-pix-aux",

				      "clk-s-stfe-frc-0",

				      "clk-s-ref-mcru",

				      "clk-s-slave-mcru",

				      "clk-s-tmds-hdmi",

				      "clk-s-hdmi-reject-pll",

				      "clk-s-thsens";

	};