Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 80213c03 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull PCI updates from Bjorn Helgaas:
 "The interesting things here are:

   - Turn on Config Request Retry Status Software Visibility.  This
     caused hangs last time, but we included a fix this time.
   - Rework PCI device configuration to use _HPP/_HPX more aggressively
   - Allow PCI devices to be put into D3cold during system suspend
   - Add arm64 PCI support
   - Add APM X-Gene host bridge driver
   - Add TI Keystone host bridge driver
   - Add Xilinx AXI host bridge driver

  More detailed summary:

  Enumeration
    - Check Vendor ID only for Config Request Retry Status (Rajat Jain)
    - Enable Config Request Retry Status when supported (Rajat Jain)
    - Add generic domain handling (Catalin Marinas)
    - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado)

  Resource management
    - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu)
    - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr)

  PCI device hotplug
    - Prevent NULL dereference during pciehp probe (Andreas Noever)
    - Move _HPP & _HPX handling into core (Bjorn Helgaas)
    - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas)
    - Apply _HPP/_HPX to display devices (Bjorn Helgaas)
    - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas)
    - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas)
    - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas)
    - Fix wait time in pciehp timeout message (Yinghai Lu)
    - Add more pciehp Slot Control debug output (Yinghai Lu)
    - Stop disabling pciehp notifications during init (Yinghai Lu)

  MSI
    - Remove arch_msi_check_device() (Alexander Gordeev)
    - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev)
    - Move D0 check into pci_msi_check_device() (Alexander Gordeev)
    - Remove unused kobject from struct msi_desc (Yijing Wang)
    - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang)
    - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang)
    - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang)
    - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang)
    - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang)

  Power management
    - Drop unused runtime PM support code for PCIe ports (Rafael J.  Wysocki)
    - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki)

  AER
    - Add additional AER error strings (Gong Chen)
    - Make <linux/aer.h> standalone includable (Thierry Reding)

  Virtualization
    - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson)
    - Add ACS quirk for Intel 10G NICs (Alex Williamson)
    - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp)
    - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson)
    - Add device flag helpers (Ethan Zhao)
    - Assume all Mellanox devices have broken INTx masking (Gavin Shan)

  Generic host bridge driver
    - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau)
    - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau)
    - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau)
    - Fix the conversion of IO ranges into IO resources (Liviu Dudau)
    - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau)
    - Add support for parsing PCI host bridge resources from DT (Liviu Dudau)
    - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau)
    - Add arm64 architectural support for PCI (Liviu Dudau)

  APM X-Gene
    - Add APM X-Gene PCIe driver (Tanmay Inamdar)
    - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar)

  Freescale i.MX6
    - Probe in module_init(), not fs_initcall() (Lucas Stach)
    - Delay enabling reference clock for SS until it stabilizes (Tim Harvey)

  Marvell MVEBU
    - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni)

  NVIDIA Tegra
    - Make sure the PCIe PLL is really reset (Eric Yuen)
    - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang)
    - Fix extended configuration space mapping (Peter Daifuku)
    - Implement resource hierarchy (Thierry Reding)
    - Clear CLKREQ# enable on port disable (Thierry Reding)
    - Add Tegra124 support (Thierry Reding)

  ST Microelectronics SPEAr13xx
    - Pass config resource through reg property (Pratyush Anand)

  Synopsys DesignWare
    - Use NULL instead of false (Fabio Estevam)
    - Parse bus-range property from devicetree (Lucas Stach)
    - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach)
    - Remove pci_assign_unassigned_resources() (Lucas Stach)
    - Check private_data validity in single place (Lucas Stach)
    - Setup and clear exactly one MSI at a time (Lucas Stach)
    - Remove open-coded bitmap operations (Lucas Stach)
    - Fix configuration base address when using 'reg' (Minghuan Lian)
    - Fix IO resource end address calculation (Minghuan Lian)
    - Rename get_msi_data() to get_msi_addr() (Minghuan Lian)
    - Add get_msi_data() to pcie_host_ops (Minghuan Lian)
    - Add support for v3.65 hardware (Murali Karicheri)
    - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand)

  TI Keystone
    - Add TI Keystone PCIe driver (Murali Karicheri)
    - Limit MRSS for all downstream devices (Murali Karicheri)
    - Assume controller is already in RC mode (Murali Karicheri)
    - Set device ID based on SoC to support multiple ports (Murali Karicheri)

  Xilinx AXI
    - Add Xilinx AXI PCIe driver (Srikanth Thokala)
    - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter)

  Miscellaneous
    - Clean up whitespace (Quentin Lambert)
    - Remove assignments from "if" conditions (Quentin Lambert)
    - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri)
    - x86: Mark DMI tables as initialization data (Mathias Krause)
    - x86: Move __init annotation to the correct place (Mathias Krause)
    - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause)
    - x86: Constify pci_mmcfg_probes[] array (Mathias Krause)
    - x86: Mark PCI BIOS initialization code as such (Mathias Krause)
    - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya)
    - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser)"

* tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (109 commits)
  arm64: dts: Add APM X-Gene PCIe device tree nodes
  PCI: Add ACS quirk for AMD A88X southbridge devices
  PCI: xgene: Add APM X-Gene PCIe driver
  PCI: designware: Remove open-coded bitmap operations
  PCI/MSI: Remove unnecessary temporary variable
  PCI/MSI: Use __write_msi_msg() instead of write_msi_msg()
  MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg()
  PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg()
  PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints
  PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
  PCI/MSI: Remove unused kobject from struct msi_desc
  PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported()
  PCI/MSI: Move D0 check into pci_msi_check_device()
  PCI/MSI: Remove arch_msi_check_device()
  irqchip: armada-370-xp: Remove arch_msi_check_device()
  PCI/MSI/PPC: Remove arch_msi_check_device()
  arm64: Add architectural support for PCI
  PCI: Add pci_remap_iospace() to map bus I/O resources
  of/pci: Add support for parsing PCI host bridge resources from DT
  of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
  ...

Conflicts:
	arch/arm64/boot/dts/apm-storm.dtsi
parents ea584595 f92d9ee3
Loading
Loading
Loading
Loading
+10 −0
Original line number Diff line number Diff line
@@ -65,6 +65,16 @@ Description:
		force a rescan of all PCI buses in the system, and
		re-discover previously removed devices.

What:		/sys/bus/pci/devices/.../msi_bus
Date:		September 2014
Contact:	Linux PCI developers <linux-pci@vger.kernel.org>
Description:
		Writing a zero value to this attribute disallows MSI and
		MSI-X for any future drivers of the device.  If the device
		is a bridge, MSI and MSI-X will be disallowed for future
		drivers of all child devices under the bridge.  Drivers
		must be reloaded for the new setting to take effect.

What:		/sys/bus/pci/devices/.../msi_irqs/
Date:		September, 2011
Contact:	Neil Horman <nhorman@tuxdriver.com>
+3 −0
Original line number Diff line number Diff line
@@ -23,3 +23,6 @@ Required properties:

Optional properties:
- reset-gpio: gpio pin number of power good signal
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
  specify this property, to keep backwards compatibility a range of 0x00-0xff
  is assumed if not present)
+24 −1
Original line number Diff line number Diff line
NVIDIA Tegra PCIe controller

Required properties:
- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
- compatible: Must be one of:
  - "nvidia,tegra20-pcie"
  - "nvidia,tegra30-pcie"
  - "nvidia,tegra124-pcie"
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
  registers. Must contain an entry for each entry in the reg-names property.
@@ -57,6 +60,11 @@ Required properties:
  - afi
  - pcie_x

Required properties on Tegra124 and later:
- phys: Must contain an entry for each entry in phy-names.
- phy-names: Must include the following entries:
  - pcie

Power supplies for Tegra20:
- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
@@ -84,6 +92,21 @@ Power supplies for Tegra30:
    - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
    - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.

Power supplies for Tegra124:
- Required:
  - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
  - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
    supply 1.05 V.
  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
    Must supply 3.3 V.
  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
    Must supply 3.3 V.
  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
    supply 2.8-3.3 V.
  - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
    supply 1.05 V.

Root ports are defined as subnodes of the PCIe controller node.

Required properties:
+63 −0
Original line number Diff line number Diff line
TI Keystone PCIe interface

Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
It shares common functions with PCIe Designware core driver and inherit
common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt

Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
for the details of Designware DT bindings.  Additional properties are
described here as well as properties that are not applicable.

Required Properties:-

compatibility: "ti,keystone-pcie"
reg:	index 1 is the base address and length of DW application registers.
	index 2 is the base address and length of PCI device ID register.

pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
	interrupt-cells: should be set to 1
	interrupt-parent: Parent interrupt controller phandle
	interrupts: GIC interrupt lines connected to PCI MSI interrupt lines

 Example:
	pcie_msi_intc: msi-interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
	};

pcie_intc: Interrupt controller device node for Legacy IRQ chip
	interrupt-cells: should be set to 1
	interrupt-parent: Parent interrupt controller phandle
	interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines

 Example:
	pcie_intc: legacy-interrupt-controller {
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
	};

Optional properties:-
	phys: phandle to Generic Keystone SerDes phy for PCI
	phy-names: name of the Generic Keystine SerDes phy for PCI
	  - If boot loader already does PCI link establishment, then phys and
	    phy-names shouldn't be present.

Designware DT Properties not applicable for Keystone PCI

1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.
+57 −0
Original line number Diff line number Diff line
* AppliedMicro X-Gene PCIe interface

Required properties:
- device_type: set to "pci"
- compatible: should contain "apm,xgene-pcie" to identify the core.
- reg: A list of physical base address and length for each set of controller
       registers. Must contain an entry for each entry in the reg-names
       property.
- reg-names: Must include the following entries:
  "csr": controller configuration registers.
  "cfg": pcie configuration space registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- ranges: ranges for the outbound memory, I/O regions.
- dma-ranges: ranges for the inbound memory regions.
- #interrupt-cells: set to <1>
- interrupt-map-mask and interrupt-map: standard PCI properties
	to define the mapping of the PCIe interface to interrupt
	numbers.
- clocks: from common clock binding: handle to pci clock.

Optional properties:
- status: Either "ok" or "disabled".
- dma-coherent: Present if dma operations are coherent

Example:

SoC specific DT Entry:

	pcie0: pcie@1f2b0000 {
		status = "disabled";
		device_type = "pci";
		compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
			0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
		reg-names = "csr", "cfg";
		ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
			  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
		dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
			      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
		interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
				 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
				 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
				 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
		dma-coherent;
		clocks = <&pcie0clk 0>;
	};


Board specific DT Entry:
	&pcie0 {
		status = "ok";
	};
Loading