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Commit 7c9cf4e3 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Reduce engine->emit_flush() to a single mode parameter 



Rather than passing a complete set of GPU cache domains for either
invalidation or for flushing, or even both, just pass a single parameter
to the engine->emit_flush to determine the required operations.

engine->emit_flush(GPU, 0) -> engine->emit_flush(EMIT_INVALIDATE)
engine->emit_flush(0, GPU) -> engine->emit_flush(EMIT_FLUSH)
engine->emit_flush(GPU, GPU) -> engine->emit_flush(EMIT_FLUSH | EMIT_INVALIDATE)

This allows us to extend the behaviour easily in future, for example if
we want just a command barrier without the overhead of flushing.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470174640-18242-8-git-send-email-chris@chris-wilson.co.uk
parent c7fe7d25

drivers/gpu/drm/i915/i915_gem_context.c

+1 −1
Original line number Diff line number Diff line
@@ -568,7 +568,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) 
	 * itlb_before_ctx_switch.

	 */

	if (IS_GEN6(dev_priv)) {

		ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);

		ret = engine->emit_flush(req, EMIT_INVALIDATE);

		if (ret)

			return ret;

	}

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+1 −1
Original line number Diff line number Diff line
@@ -999,7 +999,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, 
		wmb();



	/* Unconditionally invalidate GPU caches and TLBs. */

	return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);

	return req->engine->emit_flush(req, EMIT_INVALIDATE);

}



static bool

drivers/gpu/drm/i915/i915_gem_gtt.c

+3 −7
Original line number Diff line number Diff line
@@ -1666,8 +1666,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, 
	int ret;



	/* NB: TLBs must be flushed and invalidated before a switch */

	ret = engine->emit_flush(req,

				 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

	ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);

	if (ret)

		return ret;
@@ -1694,8 +1693,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, 
	int ret;



	/* NB: TLBs must be flushed and invalidated before a switch */

	ret = engine->emit_flush(req,

				 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

	ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);

	if (ret)

		return ret;
@@ -1713,9 +1711,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, 


	/* XXX: RCS is the only one to auto invalidate the TLBs? */

	if (engine->id != RCS) {

		ret = engine->emit_flush(req,

					 I915_GEM_GPU_DOMAINS,

					 I915_GEM_GPU_DOMAINS);

		ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);

		if (ret)

			return ret;

	}

drivers/gpu/drm/i915/i915_gem_request.c

+1 −1
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ void __i915_add_request(struct drm_i915_gem_request *request, 
	 * what.

	 */

	if (flush_caches) {

		ret = engine->emit_flush(request, 0, I915_GEM_GPU_DOMAINS);

		ret = engine->emit_flush(request, EMIT_FLUSH);



		/* Not allowed to fail! */

		WARN(ret, "engine->emit_flush() failed: %d!\n", ret);

drivers/gpu/drm/i915/intel_lrc.c

+8 −15
Original line number Diff line number Diff line
@@ -672,7 +672,7 @@ static int execlists_move_to_gpu(struct drm_i915_gem_request *req, 
	/* Unconditionally invalidate gpu caches and ensure that we do flush

	 * any residual writes from the previous batch.

	 */

	return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);

	return req->engine->emit_flush(req, EMIT_INVALIDATE);

}



int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
@@ -998,9 +998,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) 
	if (w->count == 0)

		return 0;



	ret = req->engine->emit_flush(req,

				      I915_GEM_GPU_DOMAINS,

				      I915_GEM_GPU_DOMAINS);

	ret = req->engine->emit_flush(req, EMIT_BARRIER);

	if (ret)

		return ret;
@@ -1017,9 +1015,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) 


	intel_ring_advance(ring);



	ret = req->engine->emit_flush(req,

				      I915_GEM_GPU_DOMAINS,

				      I915_GEM_GPU_DOMAINS);

	ret = req->engine->emit_flush(req, EMIT_BARRIER);

	if (ret)

		return ret;
@@ -1598,9 +1594,7 @@ static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) 
	I915_WRITE_IMR(engine, ~engine->irq_keep_mask);

}



static int gen8_emit_flush(struct drm_i915_gem_request *request,

			   u32 invalidate_domains,

			   u32 unused)

static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)

{

	struct intel_ring *ring = request->ring;

	u32 cmd;
@@ -1619,7 +1613,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request, 
	 */

	cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;



	if (invalidate_domains & I915_GEM_GPU_DOMAINS) {

	if (mode & EMIT_INVALIDATE) {

		cmd |= MI_INVALIDATE_TLB;

		if (request->engine->id == VCS)

			cmd |= MI_INVALIDATE_BSD;
@@ -1637,8 +1631,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request, 
}



static int gen8_emit_flush_render(struct drm_i915_gem_request *request,

				  u32 invalidate_domains,

				  u32 flush_domains)

				  u32 mode)

{

	struct intel_ring *ring = request->ring;

	struct intel_engine_cs *engine = request->engine;
@@ -1650,14 +1643,14 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request, 


	flags |= PIPE_CONTROL_CS_STALL;



	if (flush_domains) {

	if (mode & EMIT_FLUSH) {

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

	}



	if (invalidate_domains) {

	if (mode & EMIT_INVALIDATE) {

		flags |= PIPE_CONTROL_TLB_INVALIDATE;

		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;