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Commit c7fe7d25 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Remove obsolete engine->gpu_caches_dirty 



Space for flushing the GPU cache prior to completing the request is
preallocated and so cannot fail - the GPU caches will always be flushed
along with the completed request. This means we no longer have to track
whether the GPU cache is dirty between batches like we had to with the
outstanding_lazy_seqno.

With the removal of the duplication in the per-backend entry points for
emitting the obsolete lazy flush, we can then further unify the
engine->emit_flush.

v2: Expand a bit on the legacy of gpu_caches_dirty

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-18-git-send-email-chris@chris-wilson.co.uk


Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470174640-18242-7-git-send-email-chris@chris-wilson.co.uk
parent aad29fbb

drivers/gpu/drm/i915/i915_gem_context.c

+1 −1
Original line number Diff line number Diff line
@@ -568,7 +568,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) 
	 * itlb_before_ctx_switch.

	 */

	if (IS_GEN6(dev_priv)) {

		ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);

		ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);

		if (ret)

			return ret;

	}

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+2 −7
Original line number Diff line number Diff line
@@ -998,10 +998,8 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, 
	if (flush_domains & I915_GEM_DOMAIN_GTT)

		wmb();



	/* Unconditionally invalidate gpu caches and ensure that we do flush

	 * any residual writes from the previous batch.

	 */

	return intel_engine_invalidate_all_caches(req);

	/* Unconditionally invalidate GPU caches and TLBs. */

	return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);

}



static bool
@@ -1163,9 +1161,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas, 
static void

i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)

{

	/* Unconditionally force add_request to emit a full flush. */

	params->engine->gpu_caches_dirty = true;



	/* Add a breadcrumb for the completion of the batch buffer */

	__i915_add_request(params->request, params->batch_obj, true);

}

drivers/gpu/drm/i915/i915_gem_gtt.c

+7 −4
Original line number Diff line number Diff line
@@ -1666,7 +1666,8 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, 
	int ret;



	/* NB: TLBs must be flushed and invalidated before a switch */

	ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

	ret = engine->emit_flush(req,

				 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

	if (ret)

		return ret;
@@ -1693,7 +1694,8 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, 
	int ret;



	/* NB: TLBs must be flushed and invalidated before a switch */

	ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

	ret = engine->emit_flush(req,

				 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

	if (ret)

		return ret;
@@ -1711,8 +1713,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, 


	/* XXX: RCS is the only one to auto invalidate the TLBs? */

	if (engine->id != RCS) {

		ret = engine->flush(req,

				    I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

		ret = engine->emit_flush(req,

					 I915_GEM_GPU_DOMAINS,

					 I915_GEM_GPU_DOMAINS);

		if (ret)

			return ret;

	}

drivers/gpu/drm/i915/i915_gem_request.c

+3 −5
Original line number Diff line number Diff line
@@ -451,12 +451,10 @@ void __i915_add_request(struct drm_i915_gem_request *request, 
	 * what.

	 */

	if (flush_caches) {

		if (i915.enable_execlists)

			ret = logical_ring_flush_all_caches(request);

		else

			ret = intel_engine_flush_all_caches(request);

		ret = engine->emit_flush(request, 0, I915_GEM_GPU_DOMAINS);



		/* Not allowed to fail! */

		WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);

		WARN(ret, "engine->emit_flush() failed: %d!\n", ret);

	}



	trace_i915_gem_request_add(request);

drivers/gpu/drm/i915/intel_lrc.c

+7 −40
Original line number Diff line number Diff line
@@ -642,24 +642,6 @@ static void execlists_context_queue(struct drm_i915_gem_request *request) 
	spin_unlock_bh(&engine->execlist_lock);

}



static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)

{

	struct intel_engine_cs *engine = req->engine;

	uint32_t flush_domains;

	int ret;



	flush_domains = 0;

	if (engine->gpu_caches_dirty)

		flush_domains = I915_GEM_GPU_DOMAINS;



	ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);

	if (ret)

		return ret;



	engine->gpu_caches_dirty = false;

	return 0;

}



static int execlists_move_to_gpu(struct drm_i915_gem_request *req,

				 struct list_head *vmas)

{
@@ -690,7 +672,7 @@ static int execlists_move_to_gpu(struct drm_i915_gem_request *req, 
	/* Unconditionally invalidate gpu caches and ensure that we do flush

	 * any residual writes from the previous batch.

	 */

	return logical_ring_invalidate_all_caches(req);

	return req->engine->emit_flush(req, I915_GEM_GPU_DOMAINS, 0);

}



int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
@@ -930,22 +912,6 @@ void intel_logical_ring_stop(struct intel_engine_cs *engine) 
	I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));

}



int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)

{

	struct intel_engine_cs *engine = req->engine;

	int ret;



	if (!engine->gpu_caches_dirty)

		return 0;



	ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);

	if (ret)

		return ret;



	engine->gpu_caches_dirty = false;

	return 0;

}



static int intel_lr_context_pin(struct i915_gem_context *ctx,

				struct intel_engine_cs *engine)

{
@@ -1026,15 +992,15 @@ void intel_lr_context_unpin(struct i915_gem_context *ctx, 
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)

{

	int ret, i;

	struct intel_engine_cs *engine = req->engine;

	struct intel_ring *ring = req->ring;

	struct i915_workarounds *w = &req->i915->workarounds;



	if (w->count == 0)

		return 0;



	engine->gpu_caches_dirty = true;

	ret = logical_ring_flush_all_caches(req);

	ret = req->engine->emit_flush(req,

				      I915_GEM_GPU_DOMAINS,

				      I915_GEM_GPU_DOMAINS);

	if (ret)

		return ret;
@@ -1051,8 +1017,9 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) 


	intel_ring_advance(ring);



	engine->gpu_caches_dirty = true;

	ret = logical_ring_flush_all_caches(req);

	ret = req->engine->emit_flush(req,

				      I915_GEM_GPU_DOMAINS,

				      I915_GEM_GPU_DOMAINS);

	if (ret)

		return ret;