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Commit 75f5db39 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "Quite a lot of activity in SPI this cycle, almost all of it in drivers
  with a few minor improvements and tweaks in the core.

   - Updates to pxa2xx to support Intel Broxton and multiple chip selects.
   - Support for big endian in the bcm63xx driver.
   - Multiple slave support for the mt8173
   - New driver for the auxiliary SPI controller in bcm2835 SoCs.
   - Support for Layerscale SoCs in the Freescale DSPI driver"

* tag 'spi-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (87 commits)
  spi: pxa2xx: Rework self-initiated platform data creation for non-ACPI
  spi: pxa2xx: Add support for Intel Broxton
  spi: pxa2xx: Detect number of enabled Intel LPSS SPI chip select signals
  spi: pxa2xx: Add output control for multiple Intel LPSS chip selects
  spi: pxa2xx: Use LPSS prefix for defines that are Intel LPSS specific
  spi: Add DSPI support for layerscape family
  spi: ti-qspi: improve ->remove() callback
  spi/spi-xilinx: Fix race condition on last word read
  spi: Drop owner assignment from spi_drivers
  spi: Add THIS_MODULE to spi_driver in SPI core
  spi: Setup the master controller driver before setting the chipselect
  spi: dw: replace magic constant by DW_SPI_DR
  spi: mediatek: mt8173 spi multiple devices support
  spi: mediatek: handle controller_data in mtk_spi_setup
  spi: mediatek: remove mtk_spi_config
  spi: mediatek: Update document devicetree bindings to support multiple devices
  spi: fix kernel-doc warnings about missing return desc in spi.c
  spi: fix kernel-doc warnings about missing return desc in spi.h
  spi: pxa2xx: Align a few defines
  spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select
  ...
parents 52787e91 c70efb85

Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt

0 → 100644
+38 −0
Original line number Diff line number Diff line 
Broadcom BCM2835 auxiliar SPI1/2 controller



The BCM2835 contains two forms of SPI master controller, one known simply as

SPI0, and the other known as the "Universal SPI Master"; part of the

auxiliary block. This binding applies to the SPI1/2 controller.



Required properties:

- compatible: Should be "brcm,bcm2835-aux-spi".

- reg: Should contain register location and length for the spi block

- interrupts: Should contain shared interrupt of the aux block

- clocks: The clock feeding the SPI controller - needs to

	  point to the auxiliar clock driver of the bcm2835,

	  as this clock will enable the output gate for the specific

	  clock.

- cs-gpios: the cs-gpios (native cs is NOT supported)

	    see also spi-bus.txt



Example:



spi1@7e215080 {

	compatible = "brcm,bcm2835-aux-spi";

	reg = <0x7e215080 0x40>;

	interrupts = <1 29>;

	clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI1>;

	#address-cells = <1>;

	#size-cells = <0>;

	cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;

};



spi2@7e2150c0 {

	compatible = "brcm,bcm2835-aux-spi";

	reg = <0x7e2150c0 0x40>;

	interrupts = <1 29>;

	clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI2>;

	#address-cells = <1>;

	#size-cells = <0>;

	cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>;

};

Documentation/devicetree/bindings/spi/spi-mt65xx.txt

+6 −3
Original line number Diff line number Diff line
@@ -29,8 +29,11 @@ Required properties: 
  muxes clock, and "spi-clk" for the clock gate.



Optional properties:

-cs-gpios: see spi-bus.txt, only required for MT8173.



- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi

  controller used, this value should be 0~3, only required for MT8173.

  controller used. This is a array, the element value should be 0~3,

  only required for MT8173.

    0: specify GPIO69,70,71,72 for spi pins.

    1: specify GPIO102,103,104,105 for spi pins.

    2: specify GPIO128,129,130,131 for spi pins.
@@ -49,7 +52,7 @@ spi: spi@1100a000 { 
		 <&topckgen CLK_TOP_SPI_SEL>,

		 <&pericfg CLK_PERI_SPI0>;

	clock-names = "parent-clk", "sel-clk", "spi-clk";



	mediatek,pad-select = <0>;

	cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;

	mediatek,pad-select = <1>, <0>;

	status = "disabled";

};

arch/arm/mach-u300/dummyspichip.c

+0 −1
Original line number Diff line number Diff line
@@ -264,7 +264,6 @@ static const struct of_device_id pl022_dummy_dt_match[] = { 
static struct spi_driver pl022_dummy_driver = {

	.driver = {

		.name	= "spi-dummy",

		.owner	= THIS_MODULE,

		.of_match_table = pl022_dummy_dt_match,

	},

	.probe	= pl022_dummy_probe,

arch/mips/bcm63xx/dev-spi.c

+2 −40
Original line number Diff line number Diff line
@@ -18,29 +18,6 @@ 
#include <bcm63xx_dev_spi.h>

#include <bcm63xx_regs.h>



/*

 * register offsets

 */

static const unsigned long bcm6348_regs_spi[] = {

	__GEN_SPI_REGS_TABLE(6348)

};



static const unsigned long bcm6358_regs_spi[] = {

	__GEN_SPI_REGS_TABLE(6358)

};



const unsigned long *bcm63xx_regs_spi;

EXPORT_SYMBOL(bcm63xx_regs_spi);



static __init void bcm63xx_spi_regs_init(void)

{

	if (BCMCPU_IS_6338() || BCMCPU_IS_6348())

		bcm63xx_regs_spi = bcm6348_regs_spi;

	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||

		BCMCPU_IS_6362() || BCMCPU_IS_6368())

		bcm63xx_regs_spi = bcm6358_regs_spi;

}



static struct resource spi_resources[] = {

	{

		.start		= -1, /* filled at runtime */
@@ -53,19 +30,10 @@ static struct resource spi_resources[] = { 
	},

};



static struct bcm63xx_spi_pdata spi_pdata = {

	.bus_num		= 0,

	.num_chipselect		= 8,

};



static struct platform_device bcm63xx_spi_device = {

	.name		= "bcm63xx-spi",

	.id		= -1,

	.num_resources	= ARRAY_SIZE(spi_resources),

	.resource	= spi_resources,

	.dev		= {

		.platform_data = &spi_pdata,

	},

};



int __init bcm63xx_spi_register(void)
@@ -78,21 +46,15 @@ int __init bcm63xx_spi_register(void) 
	spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);



	if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {

		bcm63xx_spi_device.name = "bcm6348-spi",

		spi_resources[0].end += BCM_6348_RSET_SPI_SIZE - 1;

		spi_pdata.fifo_size = SPI_6348_MSG_DATA_SIZE;

		spi_pdata.msg_type_shift = SPI_6348_MSG_TYPE_SHIFT;

		spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;

	}



	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||

		BCMCPU_IS_6368()) {

		bcm63xx_spi_device.name = "bcm6358-spi",

		spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;

		spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;

		spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;

		spi_pdata.msg_ctl_width = SPI_6358_MSG_CTL_WIDTH;

	}



	bcm63xx_spi_regs_init();



	return platform_device_register(&bcm63xx_spi_device);

}

arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h

+0 −44
Original line number Diff line number Diff line
@@ -7,48 +7,4 @@ 


int __init bcm63xx_spi_register(void);



struct bcm63xx_spi_pdata {

	unsigned int	fifo_size;

	unsigned int	msg_type_shift;

	unsigned int	msg_ctl_width;

	int		bus_num;

	int		num_chipselect;

};



enum bcm63xx_regs_spi {

	SPI_CMD,

	SPI_INT_STATUS,

	SPI_INT_MASK_ST,

	SPI_INT_MASK,

	SPI_ST,

	SPI_CLK_CFG,

	SPI_FILL_BYTE,

	SPI_MSG_TAIL,

	SPI_RX_TAIL,

	SPI_MSG_CTL,

	SPI_MSG_DATA,

	SPI_RX_DATA,

};



#define __GEN_SPI_REGS_TABLE(__cpu)					\

	[SPI_CMD]		= SPI_## __cpu ##_CMD,			\

	[SPI_INT_STATUS]	= SPI_## __cpu ##_INT_STATUS,		\

	[SPI_INT_MASK_ST]	= SPI_## __cpu ##_INT_MASK_ST,		\

	[SPI_INT_MASK]		= SPI_## __cpu ##_INT_MASK,		\

	[SPI_ST]		= SPI_## __cpu ##_ST,			\

	[SPI_CLK_CFG]		= SPI_## __cpu ##_CLK_CFG,		\

	[SPI_FILL_BYTE]		= SPI_## __cpu ##_FILL_BYTE,		\

	[SPI_MSG_TAIL]		= SPI_## __cpu ##_MSG_TAIL,		\

	[SPI_RX_TAIL]		= SPI_## __cpu ##_RX_TAIL,		\

	[SPI_MSG_CTL]		= SPI_## __cpu ##_MSG_CTL,		\

	[SPI_MSG_DATA]		= SPI_## __cpu ##_MSG_DATA,		\

	[SPI_RX_DATA]		= SPI_## __cpu ##_RX_DATA,



static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)

{

	extern const unsigned long *bcm63xx_regs_spi;



	return bcm63xx_regs_spi[reg];

}



#endif /* BCM63XX_DEV_SPI_H */