Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6e677ef6 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge remote-tracking branch 'scott/next' into next 

<<
This contains a fix for a chroma_defconfig build break that was
introduced by e6500 tablewalk support, and a device tree binding patch
that missed the previous pull request due to some last-minute polishing.
>>
parents e9a37110 4b3cbc82

Documentation/devicetree/bindings/clock/corenet-clock.txt

0 → 100644
+134 −0
Original line number Diff line number Diff line 
* Clock Block on Freescale CoreNet Platforms



Freescale CoreNet chips take primary clocking input from the external

SYSCLK signal. The SYSCLK input (frequency) is multiplied using

multiple phase locked loops (PLL) to create a variety of frequencies

which can then be passed to a variety of internal logic, including

cores and peripheral IP blocks.

Please refer to the Reference Manual for details.



1. Clock Block Binding



Required properties:

- compatible: Should contain a specific clock block compatible string

	and a single chassis clock compatible string.

	Clock block strings include, but not limited to, one of the:

	* "fsl,p2041-clockgen"

	* "fsl,p3041-clockgen"

	* "fsl,p4080-clockgen"

	* "fsl,p5020-clockgen"

	* "fsl,p5040-clockgen"

	* "fsl,t4240-clockgen"

	* "fsl,b4420-clockgen"

	* "fsl,b4860-clockgen"

	Chassis clock strings include:

	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks

	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks

- reg: Describes the address of the device's resources within the

	address space defined by its parent bus, and resource zero

	represents the clock register set

- clock-frequency: Input system clock frequency



Recommended properties:

- ranges: Allows valid translation between child's address space and

	parent's. Must be present if the device has sub-nodes.

- #address-cells: Specifies the number of cells used to represent

	physical base addresses.  Must be present if the device has

	sub-nodes and set to 1 if present

- #size-cells: Specifies the number of cells used to represent

	the size of an address. Must be present if the device has

	sub-nodes and set to 1 if present



2. Clock Provider/Consumer Binding



Most of the bindings are from the common clock binding[1].

 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : Should include one of the following:

	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)

	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)

	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)

	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)

	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).

		It takes parent's clock-frequency as its clock.

	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).

		It takes parent's clock-frequency as its clock.

- #clock-cells: From common clock binding. The number of cells in a

	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"

	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.

	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single

	clock-specifier cell may take the following values:

	* 0 - equal to the PLL frequency

	* 1 - equal to the PLL frequency divided by 2

	* 2 - equal to the PLL frequency divided by 4



Recommended properties:

- clocks: Should be the phandle of input parent clock

- clock-names: From common clock binding, indicates the clock name

- clock-output-names: From common clock binding, indicates the names of

	output clocks

- reg: Should be the offset and length of clock block base address.

	The length should be 4.



Example for clock block and clock provider:

/ {

	clockgen: global-utilities@e1000 {

		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";

		ranges = <0x0 0xe1000 0x1000>;

		clock-frequency = <133333333>;

		reg = <0xe1000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-1.0";

			clock-output-names = "sysclk";

		}



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux0";

		};



		mux1: mux1@20 {

			#clock-cells = <0>;

			reg = <0x20 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux1";

		};

	};

  }



Example for clock consumer:



/ {

	cpu0: PowerPC,e5500@0 {

		...

		clocks = <&mux0>;

		...

	};

  }

arch/powerpc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -532,6 +532,7 @@ config PPC_16K_PAGES 


config PPC_64K_PAGES

	bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64

	depends on !PPC_FSL_BOOK3E

	select PPC_HAS_HASH_64K if PPC_STD_MMU_64



config PPC_256K_PAGES

arch/powerpc/mm/tlb_low_64e.S

+2 −1
Original line number Diff line number Diff line
@@ -240,6 +240,7 @@ itlb_miss_fault_bolted: 
	beq	tlb_miss_common_bolted

	b	itlb_miss_kernel_bolted



#ifdef CONFIG_PPC_FSL_BOOK3E

/*

 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.

 *
@@ -409,7 +410,7 @@ itlb_miss_fault_e6500: 
	TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)

	tlb_epilog_bolted

	b	exc_instruction_storage_book3e



#endif /* CONFIG_PPC_FSL_BOOK3E */



/**********************************************************************

 *                                                                    *

arch/powerpc/mm/tlb_nohash.c

+2 −0
Original line number Diff line number Diff line
@@ -557,10 +557,12 @@ static void setup_mmu_htw(void) 
		patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);

		patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);

		break;

#ifdef CONFIG_PPC_FSL_BOOK3E

	case PPC_HTW_E6500:

		patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);

		patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);

		break;

#endif

	}

	pr_info("MMU: Book3E HW tablewalk %s\n",

		book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");