Commit 6c4a057b authored Apr 04, 2012 by Rajendra Nayak Committed by Paul Walmsley Apr 04, 2012

ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock



All DPLLs except USB are in ALWON powerdomain. Make sure the
clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting
a DPLL relock. So, mark the database accordingly.

Without this fix, it was seen that DPLL relock fails while testing
relock in a loop of USB DPLL.

Cc: Nishanth Menon <nm@ti.com>
Tested-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

parent 91a290c4

arch/arm/mach-omap2/clock44xx_data.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -978,6 +978,7 @@ static struct clk dpll_usb_ck = {
		.recalc = &omap3_dpll_recalc,
		.round_rate = &omap2_dpll_round_rate,
		.set_rate = &omap3_noncore_dpll_set_rate,
		.clkdm_name = "l3_init_clkdm",
		};

		static struct clk dpll_usb_clkdcoldo_ck = {