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Commit 67cb49c4 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv50-/disp: audit and version PIOR_PWR method 



The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c02ed2bf

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+4 −3
Original line number Diff line number Diff line
@@ -952,6 +952,10 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd, 
			return ret;

	}

		break;

	case NV50_DISP_MTHD_V1_PIOR_PWR:

		if (!priv->pior.power)

			return -ENODEV;

		return priv->pior.power(object, priv, data, size, head, outp);

	default:

		break;

	}
@@ -1080,9 +1084,6 @@ nv50_disp_base_ofuncs = { 
static struct nouveau_omthds

nv50_disp_base_omthds[] = {

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

	{},

};

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+2 −3
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ struct nv50_disp_priv { 
	} sor;

	struct {

		int nr;

		int (*power)(struct nv50_disp_priv *, int ext, u32 data);

		int (*power)(NV50_DISP_MTHD_V1);

		u8 type[3];

	} pior;

};
@@ -99,8 +99,7 @@ int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, 


#define PIOR_MTHD(n) (n), (n) + 0x03



int nv50_pior_mthd(struct nouveau_object *, u32, void *, u32);

int nv50_pior_power(struct nv50_disp_priv *, int, u32);

int nv50_pior_power(NV50_DISP_MTHD_V1);



struct nv50_disp_base {

	struct nouveau_parent base;

drivers/gpu/drm/nouveau/core/engine/disp/nv84.c

+0 −3
Original line number Diff line number Diff line
@@ -215,9 +215,6 @@ nv84_disp_sclass[] = { 
struct nouveau_omthds

nv84_disp_base_omthds[] = {

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

	{},

};

drivers/gpu/drm/nouveau/core/engine/disp/nv94.c

+0 −3
Original line number Diff line number Diff line
@@ -74,9 +74,6 @@ nv94_disp_sclass[] = { 
static struct nouveau_omthds

nv94_disp_base_omthds[] = {

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

	{},

};

drivers/gpu/drm/nouveau/core/engine/disp/nva3.c

+0 −3
Original line number Diff line number Diff line
@@ -46,9 +46,6 @@ nva3_disp_sclass[] = { 
static struct nouveau_omthds

nva3_disp_base_omthds[] = {

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

	{},

};