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Commit c02ed2bf authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv50-/disp: audit and version SOR_DP_PWR method 



The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent a3761fa2

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+24 −0
Original line number Original line Diff line number Diff line
@@ -928,6 +928,30 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd, 
			return ret;

			return ret;

	}

	}

		break;

		break;

	case NV50_DISP_MTHD_V1_SOR_DP_PWR: {

		struct nvkm_output_dp *outpdp = (void *)outp;

		union {

			struct nv50_disp_sor_dp_pwr_v0 v0;

		} *args = data;

		nv_ioctl(object, "disp sor dp pwr size %d\n", size);

		if (nvif_unpack(args->v0, 0, 0, false)) {

			nv_ioctl(object, "disp sor dp pwr vers %d state %d\n",

				 args->v0.version, args->v0.state);

			if (args->v0.state == 0) {

				nvkm_notify_put(&outpdp->irq);

				((struct nvkm_output_dp_impl *)nv_oclass(outp))

					->lnk_pwr(outpdp, 0);

				atomic_set(&outpdp->lt.done, 0);

				return 0;

			} else

			if (args->v0.state != 0) {

				nvkm_output_dp_train(&outpdp->base, 0, true);

				return 0;

			}

		} else

			return ret;

	}

		break;

	default:

	default:

		break;

		break;

	}

	}

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -77,7 +77,6 @@ int nv84_hdmi_ctrl(NV50_DISP_MTHD_V1); 
int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1);

int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1);

int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1);

int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1);





int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);

int nv50_sor_power(NV50_DISP_MTHD_V1);

int nv50_sor_power(NV50_DISP_MTHD_V1);





int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,

int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,

drivers/gpu/drm/nouveau/core/engine/disp/nv94.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -74,7 +74,6 @@ nv94_disp_sclass[] = { 
static struct nouveau_omthds

static struct nouveau_omthds

nv94_disp_base_omthds[] = {

nv94_disp_base_omthds[] = {

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },

	{ SOR_MTHD(NV94_DISP_SOR_DP_PWR)      , nv50_sor_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

drivers/gpu/drm/nouveau/core/engine/disp/nva3.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -46,7 +46,6 @@ nva3_disp_sclass[] = { 
static struct nouveau_omthds

static struct nouveau_omthds

nva3_disp_base_omthds[] = {

nva3_disp_base_omthds[] = {

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },

	{ SOR_MTHD(NV94_DISP_SOR_DP_PWR)      , nv50_sor_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -712,7 +712,6 @@ nvd0_disp_base_ofuncs = { 
struct nouveau_omthds

struct nouveau_omthds

nvd0_disp_base_omthds[] = {

nvd0_disp_base_omthds[] = {

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nvd0_disp_base_scanoutpos },

	{ HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nvd0_disp_base_scanoutpos },

	{ SOR_MTHD(NV94_DISP_SOR_DP_PWR)      , nv50_sor_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },

	{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },