Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5f77df36 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/r6xx/r7xx: CS parser fixes 



- Drop some more safe regs taht userspace shouldn't hit
- Constant base regs need relocs.  This allows us to use
constant buffers rather than the constant register file.
Also we don't want userspace to be able to set arbitrary
mc base values for the const caches.
- Track SQ_CONFIG so we know whether userspace is using
the cfile or constant buffers.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 5898b1f3

drivers/gpu/drm/radeon/r600_cs.c

+63 −7
Original line number Original line Diff line number Diff line
@@ -45,6 +45,7 @@ struct r600_cs_track { 
	u32			nbanks;

	u32			nbanks;

	u32			npipes;

	u32			npipes;

	/* value we track */

	/* value we track */

	u32			sq_config;

	u32			nsamples;

	u32			nsamples;

	u32			cb_color_base_last[8];

	u32			cb_color_base_last[8];

	struct radeon_bo	*cb_color_bo[8];

	struct radeon_bo	*cb_color_bo[8];
@@ -141,6 +142,8 @@ static void r600_cs_track_init(struct r600_cs_track *track) 
{

{

	int i;

	int i;





	/* assume DX9 mode */

	track->sq_config = DX9_CONSTS;

	for (i = 0; i < 8; i++) {

	for (i = 0; i < 8; i++) {

		track->cb_color_base_last[i] = 0;

		track->cb_color_base_last[i] = 0;

		track->cb_color_size[i] = 0;

		track->cb_color_size[i] = 0;
@@ -715,6 +718,9 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx 
		tmp =radeon_get_ib_value(p, idx);

		tmp =radeon_get_ib_value(p, idx);

		ib[idx] = 0;

		ib[idx] = 0;

		break;

		break;

	case SQ_CONFIG:

		track->sq_config = radeon_get_ib_value(p, idx);

		break;

	case R_028800_DB_DEPTH_CONTROL:

	case R_028800_DB_DEPTH_CONTROL:

		track->db_depth_control = radeon_get_ib_value(p, idx);

		track->db_depth_control = radeon_get_ib_value(p, idx);

		break;

		break;
@@ -869,6 +875,54 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx 
	case SQ_PGM_START_VS:

	case SQ_PGM_START_VS:

	case SQ_PGM_START_GS:

	case SQ_PGM_START_GS:

	case SQ_PGM_START_PS:

	case SQ_PGM_START_PS:

	case SQ_ALU_CONST_CACHE_GS_0:

	case SQ_ALU_CONST_CACHE_GS_1:

	case SQ_ALU_CONST_CACHE_GS_2:

	case SQ_ALU_CONST_CACHE_GS_3:

	case SQ_ALU_CONST_CACHE_GS_4:

	case SQ_ALU_CONST_CACHE_GS_5:

	case SQ_ALU_CONST_CACHE_GS_6:

	case SQ_ALU_CONST_CACHE_GS_7:

	case SQ_ALU_CONST_CACHE_GS_8:

	case SQ_ALU_CONST_CACHE_GS_9:

	case SQ_ALU_CONST_CACHE_GS_10:

	case SQ_ALU_CONST_CACHE_GS_11:

	case SQ_ALU_CONST_CACHE_GS_12:

	case SQ_ALU_CONST_CACHE_GS_13:

	case SQ_ALU_CONST_CACHE_GS_14:

	case SQ_ALU_CONST_CACHE_GS_15:

	case SQ_ALU_CONST_CACHE_PS_0:

	case SQ_ALU_CONST_CACHE_PS_1:

	case SQ_ALU_CONST_CACHE_PS_2:

	case SQ_ALU_CONST_CACHE_PS_3:

	case SQ_ALU_CONST_CACHE_PS_4:

	case SQ_ALU_CONST_CACHE_PS_5:

	case SQ_ALU_CONST_CACHE_PS_6:

	case SQ_ALU_CONST_CACHE_PS_7:

	case SQ_ALU_CONST_CACHE_PS_8:

	case SQ_ALU_CONST_CACHE_PS_9:

	case SQ_ALU_CONST_CACHE_PS_10:

	case SQ_ALU_CONST_CACHE_PS_11:

	case SQ_ALU_CONST_CACHE_PS_12:

	case SQ_ALU_CONST_CACHE_PS_13:

	case SQ_ALU_CONST_CACHE_PS_14:

	case SQ_ALU_CONST_CACHE_PS_15:

	case SQ_ALU_CONST_CACHE_VS_0:

	case SQ_ALU_CONST_CACHE_VS_1:

	case SQ_ALU_CONST_CACHE_VS_2:

	case SQ_ALU_CONST_CACHE_VS_3:

	case SQ_ALU_CONST_CACHE_VS_4:

	case SQ_ALU_CONST_CACHE_VS_5:

	case SQ_ALU_CONST_CACHE_VS_6:

	case SQ_ALU_CONST_CACHE_VS_7:

	case SQ_ALU_CONST_CACHE_VS_8:

	case SQ_ALU_CONST_CACHE_VS_9:

	case SQ_ALU_CONST_CACHE_VS_10:

	case SQ_ALU_CONST_CACHE_VS_11:

	case SQ_ALU_CONST_CACHE_VS_12:

	case SQ_ALU_CONST_CACHE_VS_13:

	case SQ_ALU_CONST_CACHE_VS_14:

	case SQ_ALU_CONST_CACHE_VS_15:

		r = r600_cs_packet_next_reloc(p, &reloc);

		r = r600_cs_packet_next_reloc(p, &reloc);

		if (r) {

		if (r) {

			dev_warn(p->dev, "bad SET_CONTEXT_REG "

			dev_warn(p->dev, "bad SET_CONTEXT_REG "
@@ -1226,6 +1280,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
		}

		}

		break;

		break;

	case PACKET3_SET_ALU_CONST:

	case PACKET3_SET_ALU_CONST:

		if (track->sq_config & DX9_CONSTS) {

			start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;

			start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;

			end_reg = 4 * pkt->count + start_reg - 4;

			end_reg = 4 * pkt->count + start_reg - 4;

			if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||

			if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
@@ -1234,6 +1289,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
				DRM_ERROR("bad SET_ALU_CONST\n");

				DRM_ERROR("bad SET_ALU_CONST\n");

				return -EINVAL;

				return -EINVAL;

			}

			}

		}

		break;

		break;

	case PACKET3_SET_BOOL_CONST:

	case PACKET3_SET_BOOL_CONST:

		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;

		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;

drivers/gpu/drm/radeon/r600d.h

+49 −0
Original line number Original line Diff line number Diff line
@@ -77,6 +77,55 @@ 
#define CB_COLOR0_FRAG                                  0x280e0

#define CB_COLOR0_FRAG                                  0x280e0

#define CB_COLOR0_MASK                                  0x28100

#define CB_COLOR0_MASK                                  0x28100





#define SQ_ALU_CONST_CACHE_PS_0				0x28940

#define SQ_ALU_CONST_CACHE_PS_1				0x28944

#define SQ_ALU_CONST_CACHE_PS_2				0x28948

#define SQ_ALU_CONST_CACHE_PS_3				0x2894c

#define SQ_ALU_CONST_CACHE_PS_4				0x28950

#define SQ_ALU_CONST_CACHE_PS_5				0x28954

#define SQ_ALU_CONST_CACHE_PS_6				0x28958

#define SQ_ALU_CONST_CACHE_PS_7				0x2895c

#define SQ_ALU_CONST_CACHE_PS_8				0x28960

#define SQ_ALU_CONST_CACHE_PS_9				0x28964

#define SQ_ALU_CONST_CACHE_PS_10			0x28968

#define SQ_ALU_CONST_CACHE_PS_11			0x2896c

#define SQ_ALU_CONST_CACHE_PS_12			0x28970

#define SQ_ALU_CONST_CACHE_PS_13			0x28974

#define SQ_ALU_CONST_CACHE_PS_14			0x28978

#define SQ_ALU_CONST_CACHE_PS_15			0x2897c

#define SQ_ALU_CONST_CACHE_VS_0				0x28980

#define SQ_ALU_CONST_CACHE_VS_1				0x28984

#define SQ_ALU_CONST_CACHE_VS_2				0x28988

#define SQ_ALU_CONST_CACHE_VS_3				0x2898c

#define SQ_ALU_CONST_CACHE_VS_4				0x28990

#define SQ_ALU_CONST_CACHE_VS_5				0x28994

#define SQ_ALU_CONST_CACHE_VS_6				0x28998

#define SQ_ALU_CONST_CACHE_VS_7				0x2899c

#define SQ_ALU_CONST_CACHE_VS_8				0x289a0

#define SQ_ALU_CONST_CACHE_VS_9				0x289a4

#define SQ_ALU_CONST_CACHE_VS_10			0x289a8

#define SQ_ALU_CONST_CACHE_VS_11			0x289ac

#define SQ_ALU_CONST_CACHE_VS_12			0x289b0

#define SQ_ALU_CONST_CACHE_VS_13			0x289b4

#define SQ_ALU_CONST_CACHE_VS_14			0x289b8

#define SQ_ALU_CONST_CACHE_VS_15			0x289bc

#define SQ_ALU_CONST_CACHE_GS_0				0x289c0

#define SQ_ALU_CONST_CACHE_GS_1				0x289c4

#define SQ_ALU_CONST_CACHE_GS_2				0x289c8

#define SQ_ALU_CONST_CACHE_GS_3				0x289cc

#define SQ_ALU_CONST_CACHE_GS_4				0x289d0

#define SQ_ALU_CONST_CACHE_GS_5				0x289d4

#define SQ_ALU_CONST_CACHE_GS_6				0x289d8

#define SQ_ALU_CONST_CACHE_GS_7				0x289dc

#define SQ_ALU_CONST_CACHE_GS_8				0x289e0

#define SQ_ALU_CONST_CACHE_GS_9				0x289e4

#define SQ_ALU_CONST_CACHE_GS_10			0x289e8

#define SQ_ALU_CONST_CACHE_GS_11			0x289ec

#define SQ_ALU_CONST_CACHE_GS_12			0x289f0

#define SQ_ALU_CONST_CACHE_GS_13			0x289f4

#define SQ_ALU_CONST_CACHE_GS_14			0x289f8

#define SQ_ALU_CONST_CACHE_GS_15			0x289fc



#define	CONFIG_MEMSIZE					0x5428

#define	CONFIG_MEMSIZE					0x5428

#define CONFIG_CNTL					0x5424

#define CONFIG_CNTL					0x5424

#define	CP_STAT						0x8680

#define	CP_STAT						0x8680

drivers/gpu/drm/radeon/reg_srcs/r600

+0 −53
Original line number Original line Diff line number Diff line
@@ -280,7 +280,6 @@ r600 0x9400 
0x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE

0x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE

0x00028814 PA_SU_SC_MODE_CNTL

0x00028814 PA_SU_SC_MODE_CNTL

0x00028C08 PA_SU_VTX_CNTL

0x00028C08 PA_SU_VTX_CNTL

0x00008C00 SQ_CONFIG

0x00008C04 SQ_GPR_RESOURCE_MGMT_1

0x00008C04 SQ_GPR_RESOURCE_MGMT_1

0x00008C08 SQ_GPR_RESOURCE_MGMT_2

0x00008C08 SQ_GPR_RESOURCE_MGMT_2

0x00008C10 SQ_STACK_RESOURCE_MGMT_1

0x00008C10 SQ_STACK_RESOURCE_MGMT_1
@@ -380,54 +379,6 @@ r600 0x9400 
0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13

0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13

0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14

0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14

0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15

0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15

0x000289C0 SQ_ALU_CONST_CACHE_GS_0

0x000289C4 SQ_ALU_CONST_CACHE_GS_1

0x000289C8 SQ_ALU_CONST_CACHE_GS_2

0x000289CC SQ_ALU_CONST_CACHE_GS_3

0x000289D0 SQ_ALU_CONST_CACHE_GS_4

0x000289D4 SQ_ALU_CONST_CACHE_GS_5

0x000289D8 SQ_ALU_CONST_CACHE_GS_6

0x000289DC SQ_ALU_CONST_CACHE_GS_7

0x000289E0 SQ_ALU_CONST_CACHE_GS_8

0x000289E4 SQ_ALU_CONST_CACHE_GS_9

0x000289E8 SQ_ALU_CONST_CACHE_GS_10

0x000289EC SQ_ALU_CONST_CACHE_GS_11

0x000289F0 SQ_ALU_CONST_CACHE_GS_12

0x000289F4 SQ_ALU_CONST_CACHE_GS_13

0x000289F8 SQ_ALU_CONST_CACHE_GS_14

0x000289FC SQ_ALU_CONST_CACHE_GS_15

0x00028940 SQ_ALU_CONST_CACHE_PS_0

0x00028944 SQ_ALU_CONST_CACHE_PS_1

0x00028948 SQ_ALU_CONST_CACHE_PS_2

0x0002894C SQ_ALU_CONST_CACHE_PS_3

0x00028950 SQ_ALU_CONST_CACHE_PS_4

0x00028954 SQ_ALU_CONST_CACHE_PS_5

0x00028958 SQ_ALU_CONST_CACHE_PS_6

0x0002895C SQ_ALU_CONST_CACHE_PS_7

0x00028960 SQ_ALU_CONST_CACHE_PS_8

0x00028964 SQ_ALU_CONST_CACHE_PS_9

0x00028968 SQ_ALU_CONST_CACHE_PS_10

0x0002896C SQ_ALU_CONST_CACHE_PS_11

0x00028970 SQ_ALU_CONST_CACHE_PS_12

0x00028974 SQ_ALU_CONST_CACHE_PS_13

0x00028978 SQ_ALU_CONST_CACHE_PS_14

0x0002897C SQ_ALU_CONST_CACHE_PS_15

0x00028980 SQ_ALU_CONST_CACHE_VS_0

0x00028984 SQ_ALU_CONST_CACHE_VS_1

0x00028988 SQ_ALU_CONST_CACHE_VS_2

0x0002898C SQ_ALU_CONST_CACHE_VS_3

0x00028990 SQ_ALU_CONST_CACHE_VS_4

0x00028994 SQ_ALU_CONST_CACHE_VS_5

0x00028998 SQ_ALU_CONST_CACHE_VS_6

0x0002899C SQ_ALU_CONST_CACHE_VS_7

0x000289A0 SQ_ALU_CONST_CACHE_VS_8

0x000289A4 SQ_ALU_CONST_CACHE_VS_9

0x000289A8 SQ_ALU_CONST_CACHE_VS_10

0x000289AC SQ_ALU_CONST_CACHE_VS_11

0x000289B0 SQ_ALU_CONST_CACHE_VS_12

0x000289B4 SQ_ALU_CONST_CACHE_VS_13

0x000289B8 SQ_ALU_CONST_CACHE_VS_14

0x000289BC SQ_ALU_CONST_CACHE_VS_15

0x000288D8 SQ_PGM_CF_OFFSET_ES

0x000288D8 SQ_PGM_CF_OFFSET_ES

0x000288DC SQ_PGM_CF_OFFSET_FS

0x000288DC SQ_PGM_CF_OFFSET_FS

0x000288D4 SQ_PGM_CF_OFFSET_GS

0x000288D4 SQ_PGM_CF_OFFSET_GS
@@ -497,9 +448,7 @@ r600 0x9400 
0x0000A020 SMX_DC_CTL0

0x0000A020 SMX_DC_CTL0

0x0000A024 SMX_DC_CTL1

0x0000A024 SMX_DC_CTL1

0x0000A028 SMX_DC_CTL2

0x0000A028 SMX_DC_CTL2

0x00009608 TC_CNTL

0x00009604 TC_INVALIDATE

0x00009604 TC_INVALIDATE

0x00009490 TD_CNTL

0x00009400 TD_FILTER4

0x00009400 TD_FILTER4

0x00009404 TD_FILTER4_1

0x00009404 TD_FILTER4_1

0x00009408 TD_FILTER4_2

0x00009408 TD_FILTER4_2
@@ -829,6 +778,4 @@ r600 0x9400 
0x00009838 DB_WATERMARKS

0x00009838 DB_WATERMARKS

0x00028D28 DB_SRESULTS_COMPARE_STATE0

0x00028D28 DB_SRESULTS_COMPARE_STATE0

0x00028D44 DB_ALPHA_TO_MASK

0x00028D44 DB_ALPHA_TO_MASK

0x00009504 TA_CNTL

0x00009700 VC_CNTL
 
0x00009700 VC_CNTL
 
0x00009718 VC_CONFIG