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Commit 5c642506 authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
Browse files

MIPS: Platform files for XLR/XLS processor support 



* include/asm/netlogic added with files common for all Netlogic processors
  (common with XLP which will be added later)
* include/asm/netlogic/xlr for XLR/XLS chip specific files
* netlogic/xlr for XLR/XLS platform files

Signed-off-by: default avatarJayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2334/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent efa0f81c

arch/mips/include/asm/netlogic/interrupt.h

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/*

 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights

 * reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the NetLogic

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef _ASM_NLM_INTERRUPT_H

#define _ASM_NLM_INTERRUPT_H



/* Defines for the IRQ numbers */



#define IRQ_IPI_SMP_FUNCTION	3

#define IRQ_IPI_SMP_RESCHEDULE	4

#define IRQ_MSGRING		6

#define IRQ_TIMER		7



#endif

arch/mips/include/asm/netlogic/mips-extns.h

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/*

 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights

 * reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the NetLogic

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef _ASM_NLM_MIPS_EXTS_H

#define _ASM_NLM_MIPS_EXTS_H



/*

 * XLR and XLP interrupt request and interrupt mask registers

 */

#define read_c0_eirr()		__read_64bit_c0_register($9, 6)

#define read_c0_eimr()		__read_64bit_c0_register($9, 7)

#define write_c0_eirr(val)	__write_64bit_c0_register($9, 6, val)



/*

 * Writing EIMR in 32 bit is a special case, the lower 8 bit of the

 * EIMR is shadowed in the status register, so we cannot save and

 * restore status register for split read.

 */

#define write_c0_eimr(val)						\

do {									\

	if (sizeof(unsigned long) == 4)	{				\

		unsigned long __flags;					\

									\

		local_irq_save(__flags);				\

		__asm__ __volatile__(					\

			".set\tmips64\n\t"				\

			"dsll\t%L0, %L0, 32\n\t"			\

			"dsrl\t%L0, %L0, 32\n\t"			\

			"dsll\t%M0, %M0, 32\n\t"			\

			"or\t%L0, %L0, %M0\n\t"				\

			"dmtc0\t%L0, $9, 7\n\t"				\

			".set\tmips0"					\

			: : "r" (val));					\

		__flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\

		local_irq_restore(__flags);				\

	} else								\

		__write_64bit_c0_register($9, 7, (val));		\

} while (0)



static inline int hard_smp_processor_id(void)

{

	return __read_32bit_c0_register($15, 1) & 0x3ff;

}



#endif /*_ASM_NLM_MIPS_EXTS_H */

arch/mips/include/asm/netlogic/psb-bootinfo.h

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/*

 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights

 * reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the NetLogic

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef _ASM_NETLOGIC_BOOTINFO_H

#define _ASM_NETLOGIC_BOOTINFO_H



struct psb_info {

	uint64_t boot_level;

	uint64_t io_base;

	uint64_t output_device;

	uint64_t uart_print;

	uint64_t led_output;

	uint64_t init;

	uint64_t exit;

	uint64_t warm_reset;

	uint64_t wakeup;

	uint64_t online_cpu_map;

	uint64_t master_reentry_sp;

	uint64_t master_reentry_gp;

	uint64_t master_reentry_fn;

	uint64_t slave_reentry_fn;

	uint64_t magic_dword;

	uint64_t uart_putchar;

	uint64_t size;

	uint64_t uart_getchar;

	uint64_t nmi_handler;

	uint64_t psb_version;

	uint64_t mac_addr;

	uint64_t cpu_frequency;

	uint64_t board_version;

	uint64_t malloc;

	uint64_t free;

	uint64_t global_shmem_addr;

	uint64_t global_shmem_size;

	uint64_t psb_os_cpu_map;

	uint64_t userapp_cpu_map;

	uint64_t wakeup_os;

	uint64_t psb_mem_map;

	uint64_t board_major_version;

	uint64_t board_minor_version;

	uint64_t board_manf_revision;

	uint64_t board_serial_number;

	uint64_t psb_physaddr_map;

	uint64_t xlr_loaderip_config;

	uint64_t bldr_envp;

	uint64_t avail_mem_map;

};



enum {

	NETLOGIC_IO_SPACE = 0x10,

	PCIX_IO_SPACE,

	PCIX_CFG_SPACE,

	PCIX_MEMORY_SPACE,

	HT_IO_SPACE,

	HT_CFG_SPACE,

	HT_MEMORY_SPACE,

	SRAM_SPACE,

	FLASH_CONTROLLER_SPACE

};



#define NLM_MAX_ARGS	64

#define NLM_MAX_ENVS	32



/* This is what netlboot passes and linux boot_mem_map is subtly different */

#define NLM_BOOT_MEM_MAP_MAX	32

struct nlm_boot_mem_map {

	int nr_map;

	struct nlm_boot_mem_map_entry {

		uint64_t addr;		/* start of memory segment */

		uint64_t size;		/* size of memory segment */

		uint32_t type;		/* type of memory segment */

	} map[NLM_BOOT_MEM_MAP_MAX];

};



/* Pointer to saved boot loader info */

extern struct psb_info nlm_prom_info;



#endif

arch/mips/include/asm/netlogic/xlr/gpio.h

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/*

 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights

 * reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the NetLogic

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef _ASM_NLM_GPIO_H

#define _ASM_NLM_GPIO_H



#define NETLOGIC_GPIO_INT_EN_REG		0

#define NETLOGIC_GPIO_INPUT_INVERSION_REG	1

#define NETLOGIC_GPIO_IO_DIR_REG		2

#define NETLOGIC_GPIO_IO_DATA_WR_REG		3

#define NETLOGIC_GPIO_IO_DATA_RD_REG		4



#define NETLOGIC_GPIO_SWRESET_REG		8

#define NETLOGIC_GPIO_DRAM1_CNTRL_REG		9

#define NETLOGIC_GPIO_DRAM1_RATIO_REG		10

#define NETLOGIC_GPIO_DRAM1_RESET_REG		11

#define NETLOGIC_GPIO_DRAM1_STATUS_REG		12

#define NETLOGIC_GPIO_DRAM2_CNTRL_REG		13

#define NETLOGIC_GPIO_DRAM2_RATIO_REG		14

#define NETLOGIC_GPIO_DRAM2_RESET_REG		15

#define NETLOGIC_GPIO_DRAM2_STATUS_REG		16



#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG	21

#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG	24

#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG	25

#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG	26



#define NETLOGIC_GPIO_FUSE_BANK_REG		35

#define NETLOGIC_GPIO_CPU_RESET_REG		40

#define NETLOGIC_GPIO_RNG_REG			43



#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT	17

#define NETLOGIC_GPIO_LED_BITMAP	0x1700000

#define NETLOGIC_GPIO_LED_0_SHIFT		20

#define NETLOGIC_GPIO_LED_1_SHIFT		24



#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET	0x01

#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02

#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03

#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN	0x04



#endif

arch/mips/include/asm/netlogic/xlr/iomap.h

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/*

 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights

 * reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the NetLogic

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef _ASM_NLM_IOMAP_H

#define _ASM_NLM_IOMAP_H



#define DEFAULT_NETLOGIC_IO_BASE           CKSEG1ADDR(0x1ef00000)

#define NETLOGIC_IO_DDR2_CHN0_OFFSET       0x01000

#define NETLOGIC_IO_DDR2_CHN1_OFFSET       0x02000

#define NETLOGIC_IO_DDR2_CHN2_OFFSET       0x03000

#define NETLOGIC_IO_DDR2_CHN3_OFFSET       0x04000

#define NETLOGIC_IO_PIC_OFFSET             0x08000

#define NETLOGIC_IO_UART_0_OFFSET          0x14000

#define NETLOGIC_IO_UART_1_OFFSET          0x15100



#define NETLOGIC_IO_SIZE                   0x1000



#define NETLOGIC_IO_BRIDGE_OFFSET          0x00000



#define NETLOGIC_IO_RLD2_CHN0_OFFSET       0x05000

#define NETLOGIC_IO_RLD2_CHN1_OFFSET       0x06000



#define NETLOGIC_IO_SRAM_OFFSET            0x07000



#define NETLOGIC_IO_PCIX_OFFSET            0x09000

#define NETLOGIC_IO_HT_OFFSET              0x0A000



#define NETLOGIC_IO_SECURITY_OFFSET        0x0B000



#define NETLOGIC_IO_GMAC_0_OFFSET          0x0C000

#define NETLOGIC_IO_GMAC_1_OFFSET          0x0D000

#define NETLOGIC_IO_GMAC_2_OFFSET          0x0E000

#define NETLOGIC_IO_GMAC_3_OFFSET          0x0F000



/* XLS devices */

#define NETLOGIC_IO_GMAC_4_OFFSET          0x20000

#define NETLOGIC_IO_GMAC_5_OFFSET          0x21000

#define NETLOGIC_IO_GMAC_6_OFFSET          0x22000

#define NETLOGIC_IO_GMAC_7_OFFSET          0x23000



#define NETLOGIC_IO_PCIE_0_OFFSET          0x1E000

#define NETLOGIC_IO_PCIE_1_OFFSET          0x1F000

#define NETLOGIC_IO_SRIO_0_OFFSET          0x1E000

#define NETLOGIC_IO_SRIO_1_OFFSET          0x1F000



#define NETLOGIC_IO_USB_0_OFFSET           0x24000

#define NETLOGIC_IO_USB_1_OFFSET           0x25000



#define NETLOGIC_IO_COMP_OFFSET            0x1D000

/* end XLS devices */



/* XLR devices */

#define NETLOGIC_IO_SPI4_0_OFFSET          0x10000

#define NETLOGIC_IO_XGMAC_0_OFFSET         0x11000

#define NETLOGIC_IO_SPI4_1_OFFSET          0x12000

#define NETLOGIC_IO_XGMAC_1_OFFSET         0x13000

/* end XLR devices */



#define NETLOGIC_IO_I2C_0_OFFSET           0x16000

#define NETLOGIC_IO_I2C_1_OFFSET           0x17000



#define NETLOGIC_IO_GPIO_OFFSET            0x18000

#define NETLOGIC_IO_FLASH_OFFSET           0x19000

#define NETLOGIC_IO_TB_OFFSET              0x1C000



#define NETLOGIC_CPLD_OFFSET               KSEG1ADDR(0x1d840000)



/*

 * Base Address (Virtual) of the PCI Config address space

 * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)

 * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes

 * ie 1<<24 = 16M

 */

#define DEFAULT_PCI_CONFIG_BASE         0x18000000

#define DEFAULT_HT_TYPE0_CFG_BASE       0x16000000

#define DEFAULT_HT_TYPE1_CFG_BASE       0x17000000



#ifndef __ASSEMBLY__

#include <linux/types.h>

#include <asm/byteorder.h>



typedef volatile __u32 nlm_reg_t;

extern unsigned long netlogic_io_base;



/* FIXME read once in write_reg */

#ifdef CONFIG_CPU_LITTLE_ENDIAN

#define netlogic_read_reg(base, offset)		((base)[(offset)])

#define netlogic_write_reg(base, offset, value)	((base)[(offset)] = (value))

#else

#define netlogic_read_reg(base, offset)		(be32_to_cpu((base)[(offset)]))

#define netlogic_write_reg(base, offset, value) \

				((base)[(offset)] = cpu_to_be32((value)))

#endif



#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))

#define netlogic_write_reg_le32(base, offset, value) \

				((base)[(offset)] = cpu_to_le32((value)))

#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))

#endif /* __ASSEMBLY__ */

#endif