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Commit efa0f81c authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
Browse files

MIPS: Netlogic: Cache, TLB support and feature overrides for XLR 



CPU_XLR case added to mm/tlbex.c
CPU_XLR case added to mm/c-r4k.c for PINDEX attribute
Feature overrides for XLR cpu.

Signed-off-by: default avatarJayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2333/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3c595a51

arch/mips/include/asm/module.h

+2 −0
Original line number Diff line number Diff line
@@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr) 
#define MODULE_PROC_FAMILY "LOONGSON2 "

#elif defined CONFIG_CPU_CAVIUM_OCTEON

#define MODULE_PROC_FAMILY "OCTEON "

#elif defined CONFIG_CPU_XLR

#define MODULE_PROC_FAMILY "XLR "

#else

#error MODULE_PROC_FAMILY undefined for your processor configuration

#endif

arch/mips/mm/c-r4k.c

+1 −0
Original line number Diff line number Diff line
@@ -1006,6 +1006,7 @@ static void __cpuinit probe_pcache(void) 
	case CPU_25KF:

	case CPU_SB1:

	case CPU_SB1A:

	case CPU_XLR:

		c->dcache.flags |= MIPS_CACHE_PINDEX;

		break;

arch/mips/mm/tlbex.c

+1 −0
Original line number Diff line number Diff line
@@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, 
	case CPU_5KC:

	case CPU_TX49XX:

	case CPU_PR4450:

	case CPU_XLR:

		uasm_i_nop(p);

		tlbw(p);

		break;