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Commit 4b34bca0 authored by James Hogan's avatar James Hogan Committed by Paolo Bonzini
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MIPS: Add define for Config.VI (virtual icache) bit 



The Config.VI bit specifies that the instruction cache is virtually
tagged, which is checked in c-r4k.c's probe_pcache(). Add a proper
definition for it in mipsregs.h and make use of it.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 7414d2f6

arch/mips/include/asm/mipsregs.h

+1 −0
Original line number Diff line number Diff line
@@ -533,6 +533,7 @@ 
#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)



/* Bits specific to the MIPS32/64 PRA.	*/

#define MIPS_CONF_VI		(_ULCAST_(1) <<  3)

#define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)

#define MIPS_CONF_MT_TLB	(_ULCAST_(1) <<  7)

#define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)

arch/mips/mm/c-r4k.c

+1 −1
Original line number Diff line number Diff line
@@ -1206,7 +1206,7 @@ static void probe_pcache(void) 
			      c->icache.linesz;

		c->icache.waybit = __ffs(icache_size/c->icache.ways);



		if (config & 0x8)		/* VI bit */

		if (config & MIPS_CONF_VI)

			c->icache.flags |= MIPS_CACHE_VTAG;



		/*