Merge branches 'hwmod_devel_v3.12', 'prcm_devel_v3.12' and... (4514b4d7) · Commits · e / devices / android_kernel_teracube_2e

arch/arm/mach-omap2/cclock33xx_data.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -421,6 +421,10 @@ static struct clk aes0_fck;
		DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
		DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);

		static struct clk rng_fck;
		DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
		DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);

		/*
		* Modules clock nodes
		*
		@@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = {
		CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
		CLK(NULL, "sha0_fck", &sha0_fck),
		CLK(NULL, "aes0_fck", &aes0_fck),
		CLK(NULL, "rng_fck", &rng_fck),
		CLK(NULL, "timer1_fck", &timer1_fck),
		CLK(NULL, "timer2_fck", &timer2_fck),
		CLK(NULL, "timer3_fck", &timer3_fck),

arch/arm/mach-omap2/cclock44xx_data.c

+12 −8

Original line number	Diff line number	Diff line
		@@ -1706,6 +1706,18 @@ int __init omap4xxx_clk_init(void)

		omap2_clk_disable_autoidle_all();

		/*
		* A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
		* when its in bypass. So always lock USB before ABE DPLL.
		*/
		/*
		* Lock USB DPLL on OMAP4 devices so that the L3INIT power
		* domain can transition to retention state when not in use.
		*/
		rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
		if (rc)
		pr_err("%s: failed to configure USB DPLL!\n", __func__);

		/*
		* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
		* state when turning the ABE clock domain. Workaround this by
		@@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void)
		if (rc)
		pr_err("%s: failed to configure ABE DPLL!\n", __func__);

		/*
		* Lock USB DPLL on OMAP4 devices so that the L3INIT power
		* domain can transition to retention state when not in use.
		*/
		rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
		if (rc)
		pr_err("%s: failed to configure USB DPLL!\n", __func__);

		return 0;
		}

arch/arm/mach-omap2/omap_hwmod_33xx_data.c

+47 −22

Original line number	Diff line number	Diff line
		@@ -325,7 +325,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
		*
		* - cEFUSE (doesn't fall under any ocp_if)
		* - clkdiv32k
		* - debugss
		* - ocp watch point
		*/
		#if 0
		@@ -369,27 +368,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
		},
		};

		/*
		* 'debugss' class
		* debug sub system
		*/
		static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
		.name = "debugss",
		};

		static struct omap_hwmod am33xx_debugss_hwmod = {
		.name = "debugss",
		.class = &am33xx_debugss_hwmod_class,
		.clkdm_name = "l3_aon_clkdm",
		.main_clk = "debugss_ick",
		.prcm = {
		.omap4 = {
		.clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
		.modulemode = MODULEMODE_SWCTRL,
		},
		},
		};

		/* ocpwp */
		static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
		.name = "ocpwp",
		@@ -482,6 +460,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
		},
		};

		/*
		* 'debugss' class
		* debug sub system
		*/
		static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
		{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
		{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
		};

		static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
		.name = "debugss",
		};

		static struct omap_hwmod am33xx_debugss_hwmod = {
		.name = "debugss",
		.class = &am33xx_debugss_hwmod_class,
		.clkdm_name = "l3_aon_clkdm",
		.main_clk = "trace_clk_div_ck",
		.prcm = {
		.omap4 = {
		.clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
		.modulemode = MODULEMODE_SWCTRL,
		},
		},
		.opt_clks = debugss_opt_clks,
		.opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
		};

		/* 'smartreflex' class */
		static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
		.name = "smartreflex",
		@@ -1796,6 +1802,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
		.user = OCP_USER_MPU \| OCP_USER_SDMA,
		};

		/* l3_main -> debugss */
		static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
		{
		.pa_start = 0x4b000000,
		.pa_end = 0x4b000000 + SZ_16M - 1,
		.flags = ADDR_TYPE_RT
		},
		{ }
		};

		static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
		.master = &am33xx_l3_main_hwmod,
		.slave = &am33xx_debugss_hwmod,
		.clk = "dpll_core_m4_ck",
		.addr = am33xx_debugss_addrs,
		.user = OCP_USER_MPU,
		};

		/* l4 wkup -> smartreflex0 */
		static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
		.master = &am33xx_l4_wkup_hwmod,
		@@ -2470,6 +2494,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
		&am33xx_pruss__l3_main,
		&am33xx_wkup_m3__l4_wkup,
		&am33xx_gfx__l3_main,
		&am33xx_l3_main__debugss,
		&am33xx_l4_wkup__wkup_m3,
		&am33xx_l4_wkup__control,
		&am33xx_l4_wkup__smartreflex0,

arch/arm/mach-omap2/powerdomains3xxx_data.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -336,6 +336,13 @@ static struct powerdomain dpll5_pwrdm = {
		.voltdm = { .name = "core" },
		};

		static struct powerdomain alwon_81xx_pwrdm = {
		.name = "alwon_pwrdm",
		.prcm_offs = TI81XX_PRM_ALWON_MOD,
		.pwrsts = PWRSTS_OFF_ON,
		.voltdm = { .name = "core" },
		};

		static struct powerdomain device_81xx_pwrdm = {
		.name = "device_pwrdm",
		.prcm_offs = TI81XX_PRM_DEVICE_MOD,
		@@ -442,6 +449,7 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
		};

		static struct powerdomain *powerdomains_ti81xx[] __initdata = {
		&alwon_81xx_pwrdm,
		&device_81xx_pwrdm,
		&active_816x_pwrdm,
		&default_816x_pwrdm,

arch/arm/mach-omap2/prcm-common.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -58,6 +58,7 @@
		#define TI816X_PRM_IVAHD1_MOD 0x0d00
		#define TI816X_PRM_IVAHD2_MOD 0x0e00
		#define TI816X_PRM_SGX_MOD 0x0f00
		#define TI81XX_PRM_ALWON_MOD 0x1800

		/* 24XX register bits shared between CM & PRM registers */