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Commit 442f53fb authored by Mark Kuo's avatar Mark Kuo Committed by Thierry Reding
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clk: tegra: Fix PLLE SS coefficients 



The PLLE SS coefficients are different between Tegra210 and Tegra114.
Add SoC generation specific versions for Tegra114 and Tegra210 and use
them in their respective ->enable() callbacks.

Signed-off-by: default avatarMark Kuo <mkuo@nvidia.com>
Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent fd2963b0

drivers/clk/tegra/clk-pll.c

+12 −6
Original line number Diff line number Diff line
@@ -86,15 +86,21 @@ 
#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\

				PLLE_SS_CNTL_SSC_BYP)

#define PLLE_SS_MAX_MASK 0x1ff

#define PLLE_SS_MAX_VAL 0x25

#define PLLE_SS_MAX_VAL_TEGRA114 0x25

#define PLLE_SS_MAX_VAL_TEGRA210 0x21

#define PLLE_SS_INC_MASK (0xff << 16)

#define PLLE_SS_INC_VAL (0x1 << 16)

#define PLLE_SS_INCINTRV_MASK (0x3f << 24)

#define PLLE_SS_INCINTRV_VAL (0x20 << 24)

#define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)

#define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)

#define PLLE_SS_COEFFICIENTS_MASK \

	(PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)

#define PLLE_SS_COEFFICIENTS_VAL \

	(PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)

#define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \

	(PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\

	 PLLE_SS_INCINTRV_VAL_TEGRA114)

#define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \

	(PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\

	 PLLE_SS_INCINTRV_VAL_TEGRA210)



#define PLLE_AUX_PLLP_SEL	BIT(2)

#define PLLE_AUX_USE_LOCKDET	BIT(3)
@@ -1428,7 +1434,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	val = pll_readl(PLLE_SS_CTRL, pll);

	val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);

	val &= ~PLLE_SS_COEFFICIENTS_MASK;

	val |= PLLE_SS_COEFFICIENTS_VAL;

	val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;

	pll_writel(val, PLLE_SS_CTRL, pll);

	val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);

	pll_writel(val, PLLE_SS_CTRL, pll);
@@ -2065,7 +2071,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) 
	val = pll_readl(PLLE_SS_CTRL, pll);

	val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);

	val &= ~PLLE_SS_COEFFICIENTS_MASK;

	val |= PLLE_SS_COEFFICIENTS_VAL;

	val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;

	pll_writel(val, PLLE_SS_CTRL, pll);

	val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);

	pll_writel(val, PLLE_SS_CTRL, pll);