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Commit fd2963b0 authored by Rhyland Klein's avatar Rhyland Klein Committed by Thierry Reding
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clk: tegra: Fix typos around clearing PLLE bits during enable 



While enabling PLLE on both Tegra114 and Tegra210, we should be clearing
PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting
them. This patch fixes both places where we incorrectly set instead of
cleared those bits.

Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent f59b0168

drivers/clk/tegra/clk-pll.c

+2 −2
Original line number Diff line number Diff line
@@ -1401,7 +1401,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	val |= PLLE_MISC_IDDQ_SW_CTRL;

	val &= ~PLLE_MISC_IDDQ_SW_VALUE;

	val |= PLLE_MISC_PLLE_PTS;

	val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;

	val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);

	pll_writel_misc(val, pll);

	udelay(5);
@@ -2035,7 +2035,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) 
	val |= PLLE_MISC_IDDQ_SW_CTRL;

	val &= ~PLLE_MISC_IDDQ_SW_VALUE;

	val |= PLLE_MISC_PLLE_PTS;

	val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;

	val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);

	pll_writel_misc(val, pll);

	udelay(5);