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Commit 400b7386 authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville
Browse files

ath9k_hw: abstract the AR_PHY_AGC_CONTROL register access 



This is so we can share routines which access this register
on calib.c

Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 66860240

drivers/net/wireless/ath/ath9k/ar9002_phy.h

+0 −7
Original line number Diff line number Diff line
@@ -120,13 +120,6 @@ 
#define AR_PHY_AGC_CTL1_COARSE_HIGH      0x003F8000

#define AR_PHY_AGC_CTL1_COARSE_HIGH_S    15



#define AR_PHY_AGC_CONTROL               0x9860

#define AR_PHY_AGC_CONTROL_CAL           0x00000001

#define AR_PHY_AGC_CONTROL_NF            0x00000002

#define AR_PHY_AGC_CONTROL_ENABLE_NF     0x00008000

#define AR_PHY_AGC_CONTROL_FLTR_CAL      0x00010000

#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF  0x00020000



#define AR_PHY_CCA                  0x9864

#define AR_PHY_MINCCA_PWR           0x0FF80000

#define AR_PHY_MINCCA_PWR_S         19

drivers/net/wireless/ath/ath9k/ar9003_phy.h

+0 −13
Original line number Diff line number Diff line
@@ -359,7 +359,6 @@ 
#define AR_PHY_SWITCH_COM_2      (AR_SM_BASE + 0x8c)

#define AR_PHY_RX_CHAINMASK      (AR_SM_BASE + 0xa0)

#define AR_PHY_CAL_CHAINMASK     (AR_SM_BASE + 0xc0)

#define AR_PHY_AGC_CONTROL       (AR_SM_BASE + 0xc4)

#define AR_PHY_CALMODE           (AR_SM_BASE + 0xc8)

#define AR_PHY_FCAL_1            (AR_SM_BASE + 0xcc)

#define AR_PHY_FCAL_2_0          (AR_SM_BASE + 0xd0)
@@ -509,18 +508,6 @@ 
#define AR_PHY_GC_ENABLE_DAC_FIFO  0x00000800  /* fifo between bb and dac */

#define AR_PHY_RX_DELAY_DELAY      0x00003FFF  /* delay from wakeup to rx ena */



#define AR_PHY_AGC_CONTROL_CAL              0x00000001  /* do internal calibration */

#define AR_PHY_AGC_CONTROL_NF               0x00000002  /* do noise-floor calibration */

#define AR_PHY_AGC_CONTROL_OFFSET_CAL       0x00000800  /* allow offset calibration */

#define AR_PHY_AGC_CONTROL_ENABLE_NF        0x00008000  /* enable noise floor calibration to happen */

#define AR_PHY_AGC_CONTROL_FLTR_CAL         0x00010000  /* allow tx filter calibration */

#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF     0x00020000  /* don't update noise floor automatically */

#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS  0x00040000  /* extend noise floor power measurement */

#define AR_PHY_AGC_CONTROL_CLC_SUCCESS      0x00080000  /* carrier leak calibration done */



#define AR_PHY_AGC_CONTROL_YCOK_MAX         0x000003c0

#define AR_PHY_AGC_CONTROL_YCOK_MAX_S                6



#define AR_PHY_CALMODE_IQ           0x00000000

#define AR_PHY_CALMODE_ADC_GAIN     0x00000001

#define AR_PHY_CALMODE_ADC_DC_PER   0x00000002

drivers/net/wireless/ath/ath9k/reg.h

+15 −0
Original line number Diff line number Diff line
@@ -1776,4 +1776,19 @@ enum { 
						     * pcu_txsm.

						     */



#define AR9300_SM_BASE				0xa200

#define AR9002_PHY_AGC_CONTROL			0x9860

#define AR9003_PHY_AGC_CONTROL			AR9300_SM_BASE + 0xc4

#define AR_PHY_AGC_CONTROL			(AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)

#define AR_PHY_AGC_CONTROL_CAL			0x00000001  /* do internal calibration */

#define AR_PHY_AGC_CONTROL_NF			0x00000002  /* do noise-floor calibration */

#define AR_PHY_AGC_CONTROL_OFFSET_CAL		0x00000800  /* allow offset calibration */

#define AR_PHY_AGC_CONTROL_ENABLE_NF		0x00008000  /* enable noise floor calibration to happen */

#define AR_PHY_AGC_CONTROL_FLTR_CAL		0x00010000  /* allow tx filter calibration */

#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF		0x00020000  /* don't update noise floor automatically */

#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS	0x00040000  /* extend noise floor power measurement */

#define AR_PHY_AGC_CONTROL_CLC_SUCCESS		0x00080000  /* carrier leak calibration done */

#define AR_PHY_AGC_CONTROL_YCOK_MAX		0x000003c0

#define AR_PHY_AGC_CONTROL_YCOK_MAX_S		6



#endif