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Commit 66860240 authored by Vasanthakumar Thiagarajan's avatar Vasanthakumar Thiagarajan Committed by John W. Linville
Browse files

ath9k_hw: Initialize interrupt mask for AR9003 



Signed-off-by: default avatarVasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 55e82df4

drivers/net/wireless/ath/ath9k/hw.c

+24 −5
Original line number Diff line number Diff line
@@ -736,11 +736,23 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 
		AR_IMR_RXORN |

		AR_IMR_BCNMISC;



	if (AR_SREV_9300_20_OR_LATER(ah)) {

		imr_reg |= AR_IMR_RXOK_HP;

		if (ah->config.rx_intr_mitigation)

			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;

		else

			imr_reg |= AR_IMR_RXOK_LP;



	} else {

		if (ah->config.rx_intr_mitigation)

			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;

		else

			imr_reg |= AR_IMR_RXOK;

	}



	if (ah->config.tx_intr_mitigation)

		imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;

	else

		imr_reg |= AR_IMR_TXOK;



	if (opmode == NL80211_IFTYPE_AP)
@@ -755,6 +767,13 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);

		REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);

	}



	if (AR_SREV_9300_20_OR_LATER(ah)) {

		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);

		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);

		REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);

		REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);

	}

}



static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)

drivers/net/wireless/ath/ath9k/reg.h

+5 −0
Original line number Diff line number Diff line
@@ -1042,6 +1042,11 @@ enum { 
#define AR_PCIE_MSI                              (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)

#define AR_PCIE_MSI_ENABLE                       0x00000001



#define AR_INTR_PRIO_SYNC_ENABLE  0x40c4

#define AR_INTR_PRIO_ASYNC_MASK   0x40c8

#define AR_INTR_PRIO_SYNC_MASK    0x40cc

#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4



#define AR_RTC_9300_PLL_DIV          0x000003ff

#define AR_RTC_9300_PLL_DIV_S        0

#define AR_RTC_9300_PLL_REFDIV       0x00003C00