Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3e369b76 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira Committed by Daniel Vetter
Browse files

drm/i915: Move dpll crtc_mask and hw_state fields into separate struct 



The new struct will be used in a follow up patch to allow a current and
a staged config to exist for the same shared DPLL.

v2: Rebase on by mask_to_refcount()->hweight32() change. (Damien)

Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1e6f2ddc

drivers/gpu/drm/i915/i915_debugfs.c

+7 −6
Original line number Diff line number Diff line
@@ -2631,13 +2631,14 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) 


		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);

		seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",

			   pll->crtc_mask, pll->active, yesno(pll->on));

			   pll->config.crtc_mask, pll->active, yesno(pll->on));

		seq_printf(m, " tracked hardware state:\n");

		seq_printf(m, " dpll:    0x%08x\n", pll->hw_state.dpll);

		seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);

		seq_printf(m, " fp0:     0x%08x\n", pll->hw_state.fp0);

		seq_printf(m, " fp1:     0x%08x\n", pll->hw_state.fp1);

		seq_printf(m, " wrpll:   0x%08x\n", pll->hw_state.wrpll);

		seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);

		seq_printf(m, " dpll_md: 0x%08x\n",

			   pll->config.hw_state.dpll_md);

		seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);

		seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);

		seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);

	}

	drm_modeset_unlock_all(dev);

drivers/gpu/drm/i915/i915_drv.h

+6 −2
Original line number Diff line number Diff line
@@ -229,14 +229,18 @@ struct intel_dpll_hw_state { 
	uint32_t wrpll;

};



struct intel_shared_dpll {

struct intel_shared_dpll_config {

	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */

	struct intel_dpll_hw_state hw_state;

};



struct intel_shared_dpll {

	struct intel_shared_dpll_config config;

	int active; /* count of number of active CRTCs (i.e. DPMS on) */

	bool on; /* is the PLL actually active? Disabled during modeset */

	const char *name;

	/* should match the index in the dev_priv->shared_dplls array */

	enum intel_dpll_id id;

	struct intel_dpll_hw_state hw_state;

	/* The mode_set hook is optional and should be used together with the

	 * intel_prepare_shared_dpll function. */

	void (*mode_set)(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/intel_ddi.c

+1 −1
Original line number Diff line number Diff line
@@ -1312,7 +1312,7 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) 
static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,

			       struct intel_shared_dpll *pll)

{

	I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);

	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);

	POSTING_READ(WRPLL_CTL(pll->id));

	udelay(20);

}

drivers/gpu/drm/i915/intel_display.c

+31 −29
Original line number Diff line number Diff line
@@ -1779,7 +1779,7 @@ static void intel_prepare_shared_dpll(struct intel_crtc *crtc) 
	if (WARN_ON(pll == NULL))

		return;



	WARN_ON(!pll->crtc_mask);

	WARN_ON(!pll->config.crtc_mask);

	if (pll->active == 0) {

		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);

		WARN_ON(pll->on);
@@ -1806,7 +1806,7 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc) 
	if (WARN_ON(pll == NULL))

		return;



	if (WARN_ON(pll->crtc_mask == 0))

	if (WARN_ON(pll->config.crtc_mask == 0))

		return;



	DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
@@ -1838,7 +1838,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc) 
	if (WARN_ON(pll == NULL))

	       return;



	if (WARN_ON(pll->crtc_mask == 0))

	if (WARN_ON(pll->config.crtc_mask == 0))

		return;



	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
@@ -3846,13 +3846,13 @@ void intel_put_shared_dpll(struct intel_crtc *crtc) 
	if (pll == NULL)

		return;



	if (!(pll->crtc_mask & (1 << crtc->pipe))) {

	if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {

		WARN(1, "bad %s crtc mask\n", pll->name);

		return;

	}



	pll->crtc_mask &= ~(1 << crtc->pipe);

	if (pll->crtc_mask == 0) {

	pll->config.crtc_mask &= ~(1 << crtc->pipe);

	if (pll->config.crtc_mask == 0) {

		WARN_ON(pll->on);

		WARN_ON(pll->active);

	}
@@ -3880,7 +3880,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) 
		DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",

			      crtc->base.base.id, pll->name);



		WARN_ON(pll->crtc_mask);

		WARN_ON(pll->config.crtc_mask);



		goto found;

	}
@@ -3889,15 +3889,16 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) 
		pll = &dev_priv->shared_dplls[i];



		/* Only want to check enabled timings first */

		if (pll->crtc_mask == 0)

		if (pll->config.crtc_mask == 0)

			continue;



		if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,

			   sizeof(pll->hw_state)) == 0) {

		if (memcmp(&crtc->config.dpll_hw_state,

			   &pll->config.hw_state,

			   sizeof(pll->config.hw_state)) == 0) {

			DRM_DEBUG_KMS("CRTC:%d sharing existing %s "

				      "(crtc_mask 0x%08x, active %d)\n",

				      crtc->base.base.id, pll->name,

				      pll->crtc_mask, pll->active);

				      pll->config.crtc_mask, pll->active);



			goto found;

		}
@@ -3906,7 +3907,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) 
	/* Ok no matching timings, maybe there's a free one? */

	for (i = 0; i < dev_priv->num_shared_dpll; i++) {

		pll = &dev_priv->shared_dplls[i];

		if (pll->crtc_mask == 0) {

		if (pll->config.crtc_mask == 0) {

			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",

				      crtc->base.base.id, pll->name);

			goto found;
@@ -3916,14 +3917,14 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) 
	return NULL;



found:

	if (pll->crtc_mask == 0)

		pll->hw_state = crtc->config.dpll_hw_state;

	if (pll->config.crtc_mask == 0)

		pll->config.hw_state = crtc->config.dpll_hw_state;



	crtc->config.shared_dpll = i;

	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,

			 pipe_name(crtc->pipe));



	pll->crtc_mask |= 1 << crtc->pipe;

	pll->config.crtc_mask |= 1 << crtc->pipe;



	return pll;

}
@@ -10606,9 +10607,9 @@ check_shared_dpll_state(struct drm_device *dev) 


		active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);



		WARN(pll->active > hweight32(pll->crtc_mask),

		WARN(pll->active > hweight32(pll->config.crtc_mask),

		     "more active pll users than references: %i vs %i\n",

		     pll->active, hweight32(pll->crtc_mask));

		     pll->active, hweight32(pll->config.crtc_mask));

		WARN(pll->active && !pll->on,

		     "pll in active use but not on in sw tracking\n");

		WARN(pll->on && !pll->active,
@@ -10626,11 +10627,11 @@ check_shared_dpll_state(struct drm_device *dev) 
		WARN(pll->active != active_crtcs,

		     "pll active crtcs mismatch (expected %i, found %i)\n",

		     pll->active, active_crtcs);

		WARN(hweight32(pll->crtc_mask) != enabled_crtcs,

		WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,

		     "pll enabled crtcs mismatch (expected %i, found %i)\n",

		     hweight32(pll->crtc_mask), enabled_crtcs);

		     hweight32(pll->config.crtc_mask), enabled_crtcs);



		WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,

		WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,

				       sizeof(dpll_hw_state)),

		     "pll hw state mismatch\n");

	}
@@ -11305,8 +11306,8 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, 
static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,

				  struct intel_shared_dpll *pll)

{

	I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);

	I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);

	I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);

	I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);

}



static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
@@ -11315,7 +11316,7 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, 
	/* PCH refclock must be enabled first */

	ibx_assert_pch_refclk_enabled(dev_priv);



	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);

	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);



	/* Wait for the clocks to stabilize. */

	POSTING_READ(PCH_DPLL(pll->id));
@@ -11326,7 +11327,7 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, 
	 *

	 * So write it again.

	 */

	I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);

	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);

	POSTING_READ(PCH_DPLL(pll->id));

	udelay(200);

}
@@ -13077,20 +13078,21 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) 
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {

		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];



		pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);

		pll->on = pll->get_hw_state(dev_priv, pll,

					    &pll->config.hw_state);

		pll->active = 0;

		pll->crtc_mask = 0;

		pll->config.crtc_mask = 0;

		for_each_intel_crtc(dev, crtc) {

			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {

				pll->active++;

				pll->crtc_mask |= 1 << crtc->pipe;

				pll->config.crtc_mask |= 1 << crtc->pipe;

			}

		}



		DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",

			      pll->name, pll->crtc_mask, pll->on);

			      pll->name, pll->config.crtc_mask, pll->on);



		if (pll->crtc_mask)

		if (pll->config.crtc_mask)

			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);

	}