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Commit 312cec5d authored by Russell King's avatar Russell King Committed by Russell King
Browse files

Merge branch 'omap-clock-for-next' of git://git.pwsan.com/linux-2.6 into devel

parents 48ec2b53 2687069f

arch/arm/mach-omap2/clock.c

+1 −1
Original line number Diff line number Diff line
@@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) 
		udelay(1);

	}



	if (i < MAX_CLOCK_ENABLE_WAIT)

	if (i <= MAX_CLOCK_ENABLE_WAIT)

		pr_debug("Clock %s stable after %d loops\n", name, i);

	else

		printk(KERN_ERR "Clock %s didn't enable in %d tries\n",

arch/arm/mach-omap2/clock34xx.c

+31 −11
Original line number Diff line number Diff line
@@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = { 


#define MIN_SDRC_DLL_LOCK_FREQ		83000000



#define CYCLES_PER_MHZ			1000000



/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */

#define SDRC_MPURATE_SCALE		8



/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */

#define SDRC_MPURATE_BASE_SHIFT		9



/*

 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at

 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize

 */

#define SDRC_MPURATE_LOOPS		96



/**

 * omap3_dpll_recalc - recalculate DPLL rate

 * @clk: DPLL struct clk
@@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) 
{

	u32 new_div = 0;

	u32 unlock_dll = 0;

	unsigned long validrate, sdrcrate;

	u32 c;

	unsigned long validrate, sdrcrate, mpurate;

	struct omap_sdrc_params *sp;



	if (!clk || !rate)
@@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) 
	if (clk != &dpll3_m2_ck)

		return -EINVAL;



	if (rate == clk->rate)

		return 0;



	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);

	if (validrate != rate)

		return -EINVAL;



	sdrcrate = sdrc_ick.rate;

	if (rate > clk->rate)

		sdrcrate <<= ((rate / clk->rate) - 1);

		sdrcrate <<= ((rate / clk->rate) >> 1);

	else

		sdrcrate >>= ((clk->rate / rate) - 1);

		sdrcrate >>= ((clk->rate / rate) >> 1);



	sp = omap2_sdrc_get_params(sdrcrate);

	if (!sp)
@@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) 
		unlock_dll = 1;

	}



	/*

	 * XXX This only needs to be done when the CPU frequency changes

	 */

	mpurate = arm_fck.rate / CYCLES_PER_MHZ;

	c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;

	c += 1;  /* for safety */

	c *= SDRC_MPURATE_LOOPS;

	c >>= SDRC_MPURATE_SCALE;

	if (c == 0)

		c = 1;



	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,

		 validrate);

	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",

		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);



	/* REVISIT: SRAM code doesn't support other M2 divisors yet */

	WARN_ON(new_div != 1 && new_div != 2);



	/* REVISIT: Add SDRC_MR changing to this code also */

	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,

				  sp->actim_ctrlb, new_div, unlock_dll);

				  sp->actim_ctrlb, new_div, unlock_dll, c,

				  sp->mr, rate > clk->rate);



	return 0;

}

arch/arm/mach-omap2/io.c

+36 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/clk.h>



#include <asm/tlb.h>
@@ -241,6 +242,40 @@ void __init omap2_map_common_io(void) 
	omapfb_reserve_sdram();

}



/*

 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters

 *

 * Sets the CORE DPLL3 M2 divider to the same value that it's at

 * currently.  This has the effect of setting the SDRC SDRAM AC timing

 * registers to the values currently defined by the kernel.  Currently

 * only defined for OMAP3; will return 0 if called on OMAP2.  Returns

 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,

 * or passes along the return value of clk_set_rate().

 */

static int __init _omap2_init_reprogram_sdrc(void)

{

	struct clk *dpll3_m2_ck;

	int v = -EINVAL;

	long rate;



	if (!cpu_is_omap34xx())

		return 0;



	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");

	if (!dpll3_m2_ck)

		return -EINVAL;



	rate = clk_get_rate(dpll3_m2_ck);

	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);

	v = clk_set_rate(dpll3_m2_ck, rate);

	if (v)

		pr_err("dpll3_m2_clk rate change failed: %d\n", v);



	clk_put(dpll3_m2_ck);



	return v;

}



void __init omap2_init_common_hw(struct omap_sdrc_params *sp)

{

	omap2_mux_init();
@@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp) 
	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);

	omap2_clk_init();

	omap2_sdrc_init(sp);

	_omap2_init_reprogram_sdrc();

#endif

	gpmc_init();

}

arch/arm/mach-omap2/powerdomain.c

+1 −1
Original line number Diff line number Diff line
@@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) 
	       (c++ < PWRDM_TRANSITION_BAILOUT))

		udelay(1);



	if (c >= PWRDM_TRANSITION_BAILOUT) {

	if (c > PWRDM_TRANSITION_BAILOUT) {

		printk(KERN_ERR "powerdomain: waited too long for "

		       "powerdomain %s to complete transition\n", pwrdm->name);

		return -EAGAIN;

arch/arm/mach-omap2/sram34xx.S

+85 −44
Original line number Diff line number Diff line
@@ -3,13 +3,12 @@ 
 *

 * Omap3 specific functions that need to be run in internal SRAM

 *

 * (C) Copyright 2007

 * Texas Instruments Inc.

 * Rajendra Nayak <rnayak@ti.com>

 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.

 * Copyright (C) 2008 Nokia Corporation

 *

 * (C) Copyright 2004

 * Texas Instruments, <www.ti.com>

 * Rajendra Nayak <rnayak@ti.com>

 * Richard Woodruff <r-woodruff2@ti.com>

 * Paul Walmsley

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as
@@ -37,61 +36,112 @@ 


	.text



/* r4 parameters */

#define SDRC_NO_UNLOCK_DLL		0x0

#define SDRC_UNLOCK_DLL			0x1



/* SDRC_DLLA_CTRL bit settings */

#define FIXEDDELAY_SHIFT		24

#define FIXEDDELAY_MASK			(0xff << FIXEDDELAY_SHIFT)

#define DLLIDLE_MASK			0x4



/*

 * SDRC_DLLA_CTRL default values: TI hardware team indicates that

 * FIXEDDELAY should be initialized to 0xf.  This apparently was

 * empirically determined during process testing, so no derivation

 * was provided.

 */

#define FIXEDDELAY_DEFAULT		(0x0f << FIXEDDELAY_SHIFT)



/* SDRC_DLLA_STATUS bit settings */

#define LOCKSTATUS_MASK			0x4



/* SDRC_POWER bit settings */

#define SRFRONIDLEREQ_MASK		0x40

#define PWDENA_MASK			0x4



/* CM_IDLEST1_CORE bit settings */

#define ST_SDRC_MASK			0x2



/* CM_ICLKEN1_CORE bit settings */

#define EN_SDRC_MASK			0x2



/* CM_CLKSEL1_PLL bit settings */

#define CORE_DPLL_CLKOUT_DIV_SHIFT	0x1b



/*

 * Change frequency of core dpll

 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2

 * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for

 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider

 * r0 = new SDRC_RFR_CTRL register contents

 * r1 = new SDRC_ACTIM_CTRLA register contents

 * r2 = new SDRC_ACTIM_CTRLB register contents

 * r3 = new M2 divider setting (only 1 and 2 supported right now)

 * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for

 *      SDRC rates < 83MHz

 * r5 = number of MPU cycles to wait for SDRC to stabilize after

 *      reprogramming the SDRC when switching to a slower MPU speed

 * r6 = new SDRC_MR_0 register value

 * r7 = increasing SDRC rate? (1 = yes, 0 = no)

 *

 */

ENTRY(omap3_sram_configure_core_dpll)

	stmfd	sp!, {r1-r12, lr}	@ store regs to stack

	ldr	r4, [sp, #52]		@ pull extra args off the stack

	ldr	r5, [sp, #56]		@ load extra args from the stack

	ldr	r6, [sp, #60]		@ load extra args from the stack

	ldr	r7, [sp, #64]		@ load extra args from the stack

	dsb				@ flush buffered writes to interconnect

	cmp	r3, #0x2

	blne	configure_sdrc

	cmp	r4, #0x1

	cmp	r7, #1			@ if increasing SDRC clk rate,

	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)

	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state

	bleq	unlock_dll

	blne	lock_dll

	bl	sdram_in_selfrefresh	@ put the SDRAM in self refresh

	bl 	configure_core_dpll

	bl	enable_sdrc

	cmp	r4, #0x1

	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC

	bl 	configure_core_dpll	@ change the DPLL3 M2 divider

	bl	enable_sdrc		@ take SDRC out of idle

	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change

	bleq	wait_dll_unlock

	blne	wait_dll_lock

	cmp	r3, #0x1

	blne	configure_sdrc

	cmp	r7, #1			@ if increasing SDRC clk rate,

	beq	return_to_sdram		@ return to SDRAM code, otherwise,

	bl	configure_sdrc		@ reprogram SDRC regs now

	mov	r12, r5

	bl	wait_clk_stable		@ wait for SDRC to stabilize

return_to_sdram:

	isb				@ prevent speculative exec past here

	mov 	r0, #0 			@ return value

	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return

unlock_dll:

	ldr	r11, omap3_sdrc_dlla_ctrl

	ldr	r12, [r11]

	orr	r12, r12, #0x4

	and	r12, r12, #FIXEDDELAY_MASK

	orr	r12, r12, #FIXEDDELAY_DEFAULT

	orr	r12, r12, #DLLIDLE_MASK

	str	r12, [r11]		@ (no OCP barrier needed)

	bx	lr

lock_dll:

	ldr	r11, omap3_sdrc_dlla_ctrl

	ldr	r12, [r11]

	bic	r12, r12, #0x4

	bic	r12, r12, #DLLIDLE_MASK

	str	r12, [r11]		@ (no OCP barrier needed)

	bx	lr

sdram_in_selfrefresh:

	ldr	r11, omap3_sdrc_power	@ read the SDRC_POWER register

	ldr	r12, [r11]		@ read the contents of SDRC_POWER

	mov	r9, r12			@ keep a copy of SDRC_POWER bits

	orr 	r12, r12, #0x40		@ enable self refresh on idle req

	bic 	r12, r12, #0x4		@ clear PWDENA

	orr 	r12, r12, #SRFRONIDLEREQ_MASK	@ enable self refresh on idle

	bic 	r12, r12, #PWDENA_MASK	@ clear PWDENA

	str 	r12, [r11]		@ write back to SDRC_POWER register

	ldr	r12, [r11]		@ posted-write barrier for SDRC

idle_sdrc:

	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg

	ldr	r12, [r11]

	bic	r12, r12, #0x2		@ disable iclk bit for SDRC

	bic	r12, r12, #EN_SDRC_MASK		@ disable iclk bit for SDRC

	str 	r12, [r11]

wait_sdrc_idle:

	ldr 	r11, omap3_cm_idlest1_core

	ldr 	r12, [r11]

	and 	r12, r12, #0x2		@ check for SDRC idle

	cmp 	r12, #2

	and 	r12, r12, #ST_SDRC_MASK		@ check for SDRC idle

	cmp 	r12, #ST_SDRC_MASK

	bne 	wait_sdrc_idle

	bx 	lr

configure_core_dpll:
@@ -99,36 +149,23 @@ configure_core_dpll: 
	ldr	r12, [r11]

	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll

	and	r12, r12, r10

	orr	r12, r12, r3, lsl #0x1B	@ r3 contains the M2 val

	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT

	str	r12, [r11]

	ldr	r12, [r11]		@ posted-write barrier for CM

	mov 	r12, #0x800		@ wait for the clock to stabilise

	cmp	r3, #2

	bne	wait_clk_stable

	bx	lr

wait_clk_stable:

	subs 	r12, r12, #1

	bne	wait_clk_stable

	nop

	nop

	nop

	nop

	nop

	nop

	nop

	nop

	nop

	nop

	bx	lr

enable_sdrc:

	ldr 	r11, omap3_cm_iclken1_core

	ldr	r12, [r11]

	orr 	r12, r12, #0x2		@ enable iclk bit for SDRC

	orr 	r12, r12, #EN_SDRC_MASK		@ enable iclk bit for SDRC

	str 	r12, [r11]

wait_sdrc_idle1:

	ldr 	r11, omap3_cm_idlest1_core

	ldr	r12, [r11]

	and 	r12, r12, #0x2

	and 	r12, r12, #ST_SDRC_MASK

	cmp	r12, #0

	bne	wait_sdrc_idle1

restore_sdrc_power_val:
@@ -138,14 +175,14 @@ restore_sdrc_power_val: 
wait_dll_lock:

	ldr	r11, omap3_sdrc_dlla_status

	ldr	r12, [r11]

	and 	r12, r12, #0x4

	cmp	r12, #0x4

	and 	r12, r12, #LOCKSTATUS_MASK

	cmp	r12, #LOCKSTATUS_MASK

	bne	wait_dll_lock

	bx	lr

wait_dll_unlock:

	ldr	r11, omap3_sdrc_dlla_status

	ldr	r12, [r11]

	and	r12, r12, #0x4

	and	r12, r12, #LOCKSTATUS_MASK

	cmp	r12, #0x0

	bne	wait_dll_unlock

	bx	lr
@@ -156,7 +193,9 @@ configure_sdrc: 
	str	r1, [r11]

	ldr	r11, omap3_sdrc_actim_ctrlb

	str	r2, [r11]

	ldr	r2, [r11]		@ posted-write barrier for SDRC

	ldr	r11, omap3_sdrc_mr_0

	str	r6, [r11]

	ldr	r6, [r11]		@ posted-write barrier for SDRC

	bx	lr



omap3_sdrc_power:
@@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla: 
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)

omap3_sdrc_actim_ctrlb:

	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)

omap3_sdrc_mr_0:

	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)

omap3_sdrc_dlla_status:

	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)

omap3_sdrc_dlla_ctrl: