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Commit 263b30d4 authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Daniel Vetter
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drm/i915: Fix HSW power well control state read 



Fix power well control state by reading real register offset.

Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 14f86147

drivers/gpu/drm/i915/intel_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -3842,7 +3842,7 @@ void intel_init_power_wells(struct drm_device *dev) 


		if ((well & HSW_PWR_WELL_STATE) == 0) {

			I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);

			if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))

			if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))

				DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);

		}

	}