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Commit 14f86147 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
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drm/i915: Flush using only the correct base address register 



We were writing DSP_ADDR and DSP_SURF unconditionally. This did not
trigger an unclaimed write before HSW as the address of DSP_ADDR has
been repurposed as DSP_LINOFF.

On HSW, though, DSP_LINOFF has been removed and then writting to it
triggers an unclaimed write.

This patch writes to DSP_ADDR or DSP_SURF to flush the display plane
configuration depending on the gen we're running on.

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4358a374

drivers/gpu/drm/i915/intel_display.c

+4 −2
Original line number Diff line number Diff line
@@ -1836,8 +1836,10 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, 
void intel_flush_display_plane(struct drm_i915_private *dev_priv,

				      enum plane plane)

{

	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));

	if (dev_priv->info->gen >= 4)

		I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));

	else

		I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));

}



/**