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Commit 4358a374 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: implement WaDisableRenderCachePipelinedFlush 



Comment says for eaglelake/cantiga, but it's listed in the ilk table,
too. So apply it to both.

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a8b1397d

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -670,6 +670,7 @@ 
#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */



#define CACHE_MODE_0	0x02120 /* 915+ only */

#define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)

#define   CM0_IZ_OPT_DISABLE      (1<<6)

#define   CM0_ZR_OPT_DISABLE      (1<<5)

#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)

drivers/gpu/drm/i915/intel_pm.c

+8 −0
Original line number Diff line number Diff line
@@ -3382,6 +3382,10 @@ static void ironlake_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(_3D_CHICKEN2,

		   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |

		   _3D_CHICKEN2_WM_READ_PIPELINED);



	/* WaDisableRenderCachePipelinedFlush */

	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));

}



static void gen6_init_clock_gating(struct drm_device *dev)
@@ -3716,6 +3720,10 @@ static void g4x_init_clock_gating(struct drm_device *dev) 
	if (IS_GM45(dev))

		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;

	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);



	/* WaDisableRenderCachePipelinedFlush */

	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));

}



static void crestline_init_clock_gating(struct drm_device *dev)