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Commit 1c27df1c authored by Will Deacon's avatar Will Deacon
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iommu/arm-smmu: Use correct address mask for CMD_TLBI_S2_IPA 



Stage-2 TLBI by IPA takes a 48-bit address field, as opposed to the
64-bit field used by the VA-based invalidation commands.

This patch re-jigs the SMMUv3 command construction code so that the
address field is correctly masked.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent f0c453db

drivers/iommu/arm-smmu-v3.c

+6 −3
Original line number Diff line number Diff line
@@ -343,7 +343,8 @@ 
#define CMDQ_TLBI_0_VMID_SHIFT		32

#define CMDQ_TLBI_0_ASID_SHIFT		48

#define CMDQ_TLBI_1_LEAF		(1UL << 0)

#define CMDQ_TLBI_1_ADDR_MASK		~0xfffUL

#define CMDQ_TLBI_1_VA_MASK		~0xfffUL

#define CMDQ_TLBI_1_IPA_MASK		0xfffffffff000UL



#define CMDQ_PRI_0_SSID_SHIFT		12

#define CMDQ_PRI_0_SSID_MASK		0xfffffUL
@@ -771,11 +772,13 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) 
		break;

	case CMDQ_OP_TLBI_NH_VA:

		cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;

		/* Fallthrough */

		cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;

		cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;

		break;

	case CMDQ_OP_TLBI_S2_IPA:

		cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;

		cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;

		cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_ADDR_MASK;

		cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;

		break;

	case CMDQ_OP_TLBI_NH_ASID:

		cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;