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Commit f0c453db authored by Will Deacon's avatar Will Deacon
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iommu/arm-smmu: Ensure IAS is set correctly for AArch32-capable SMMUs 



AArch32-capable SMMU implementations have a minimum IAS of 40 bits, so
ensure that is reflected in the stage-2 page table configuration.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent ffcb6d16

drivers/iommu/arm-smmu-v3.c

+9 −3
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ 
#define IDR0_TTF_SHIFT			2

#define IDR0_TTF_MASK			0x3

#define IDR0_TTF_AARCH64		(2 << IDR0_TTF_SHIFT)

#define IDR0_TTF_AARCH32_64		(3 << IDR0_TTF_SHIFT)

#define IDR0_S1P			(1 << 1)

#define IDR0_S2P			(1 << 0)
@@ -2460,7 +2461,13 @@ static int arm_smmu_device_probe(struct arm_smmu_device *smmu) 
	}



	/* We only support the AArch64 table format at present */

	if ((reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) < IDR0_TTF_AARCH64) {

	switch (reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) {

	case IDR0_TTF_AARCH32_64:

		smmu->ias = 40;

		/* Fallthrough */

	case IDR0_TTF_AARCH64:

		break;

	default:

		dev_err(smmu->dev, "AArch64 table format not supported!\n");

		return -ENXIO;

	}
@@ -2541,8 +2548,7 @@ static int arm_smmu_device_probe(struct arm_smmu_device *smmu) 
		dev_warn(smmu->dev,

			 "failed to set DMA mask for table walker\n");



	if (!smmu->ias)

		smmu->ias = smmu->oas;

	smmu->ias = max(smmu->ias, smmu->oas);



	dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n",

		 smmu->ias, smmu->oas, smmu->features);