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Commit 0f477dd0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip 

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86: Fix keeping track of AMD C1E
  x86, cpu: Package Level Thermal Control, Power Limit Notification definitions
  x86, cpu: Export AMD errata definitions
  x86, cpu: Use AMD errata checking framework for erratum 383
  x86, cpu: Clean up AMD erratum 400 workaround
  x86, cpu: AMD errata checking framework
  x86, cpu: Split addon_cpuid_features.c
  x86, cpu: Clean up formatting in cpufeature.h, remove override
  x86, cpu: Enumerate xsaveopt
  x86, cpu: Add xsaveopt cpufeature
  x86, cpu: Make init_scattered_cpuid_features() consider cpuid subleaves
  x86, cpu: Support the features flags in new CPUID leaf 7
  x86, cpu: Add CPU flags for F16C and RDRND
  x86: Look for IA32_ENERGY_PERF_BIAS support
  x86, AMD: Extend support to future families
  x86, cacheinfo: Carve out L3 cache slot accessors
  x86, xsave: Cleanup return codes in check_for_xstate()
parents c4efd6b5 e8c534ec

arch/x86/include/asm/acpi.h

+1 −1
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) 
	    boot_cpu_data.x86_model <= 0x05 &&

	    boot_cpu_data.x86_mask < 0x0A)

		return 1;

	else if (boot_cpu_has(X86_FEATURE_AMDC1E))

	else if (c1e_detected)

		return 1;

	else

		return max_cstate;

arch/x86/include/asm/cpufeature.h

+20 −9
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 


#include <asm/required-features.h>



#define NCAPINTS	9	/* N 32-bit words worth of info */

#define NCAPINTS	10	/* N 32-bit words worth of info */



/*

 * Note: If the comment begins with a quoted string, that string is used
@@ -89,7 +89,7 @@ 
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */

#define X86_FEATURE_11AP	(3*32+19) /* "" Bad local APIC aka 11AP */

#define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */

#define X86_FEATURE_AMDC1E	(3*32+21) /* AMD C1E detected */

					  /* 21 available, was AMD_C1E */

#define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */

#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */

#define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */
@@ -124,6 +124,8 @@ 
#define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */

#define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */

#define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */

#define X86_FEATURE_F16C	(4*32+29) /* 16-bit fp conversions */

#define X86_FEATURE_RDRND	(4*32+30) /* The RDRAND instruction */

#define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running on a hypervisor */



/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
@@ -157,13 +159,17 @@ 


/*

 * Auxiliary flags: Linux defined - For features scattered in various

 * CPUID levels like 0x6, 0xA etc

 * CPUID levels like 0x6, 0xA etc, word 7

 */

#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */

#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */

#define X86_FEATURE_CPB		(7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		(7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_XSAVEOPT	(7*32+ 4) /* Optimized Xsave */

#define X86_FEATURE_PLN		(7*32+ 5) /* Intel Power Limit Notification */

#define X86_FEATURE_PTS		(7*32+ 6) /* Intel Package Thermal Status */



/* Virtualization flags: Linux defined */

/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */

#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */

#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
@@ -174,6 +180,9 @@ 
#define X86_FEATURE_SVML	(8*32+ 7) /* "svm_lock" AMD SVM locking MSR */

#define X86_FEATURE_NRIPS	(8*32+ 8) /* "nrip_save" AMD SVM next_rip save */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */

#define X86_FEATURE_FSGSBASE	(9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/



#if defined(__KERNEL__) && !defined(__ASSEMBLY__)



#include <asm/asm.h>
@@ -194,7 +203,9 @@ extern const char * const x86_power_flags[32]; 
	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\

	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\

	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||	\

	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )	\

	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ||	\

	   (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) ||	\

	   (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )	\

	  ? 1 :								\

	 test_cpu_cap(c, bit))

arch/x86/include/asm/msr-index.h

+17 −2
Original line number Diff line number Diff line
@@ -226,12 +226,14 @@ 
#define MSR_IA32_THERM_CONTROL		0x0000019a

#define MSR_IA32_THERM_INTERRUPT	0x0000019b



#define THERM_INT_LOW_ENABLE		(1 << 0)

#define THERM_INT_HIGH_ENABLE		(1 << 1)

#define THERM_INT_HIGH_ENABLE		(1 << 0)

#define THERM_INT_LOW_ENABLE		(1 << 1)

#define THERM_INT_PLN_ENABLE		(1 << 24)



#define MSR_IA32_THERM_STATUS		0x0000019c



#define THERM_STATUS_PROCHOT		(1 << 0)

#define THERM_STATUS_POWER_LIMIT	(1 << 10)



#define MSR_THERM2_CTL			0x0000019d
@@ -241,6 +243,19 @@ 


#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2



#define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0



#define MSR_IA32_PACKAGE_THERM_STATUS		0x000001b1



#define PACKAGE_THERM_STATUS_PROCHOT		(1 << 0)

#define PACKAGE_THERM_STATUS_POWER_LIMIT	(1 << 10)



#define MSR_IA32_PACKAGE_THERM_INTERRUPT	0x000001b2



#define PACKAGE_THERM_INT_HIGH_ENABLE		(1 << 0)

#define PACKAGE_THERM_INT_LOW_ENABLE		(1 << 1)

#define PACKAGE_THERM_INT_PLN_ENABLE		(1 << 24)



/* MISC_ENABLE bits: architectural */

#define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)

#define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)

arch/x86/include/asm/processor.h

+21 −0
Original line number Diff line number Diff line
@@ -762,6 +762,7 @@ extern void init_c1e_mask(void); 
extern unsigned long		boot_option_idle_override;

extern unsigned long		idle_halt;

extern unsigned long		idle_nomwait;

extern bool			c1e_detected;



/*

 * on systems with caches, caches must be flashed as the absolute
@@ -1025,4 +1026,24 @@ unsigned long calc_aperfmperf_ratio(struct aperfmperf *old, 
	return ratio;

}



/*

 * AMD errata checking

 */

#ifdef CONFIG_CPU_SUP_AMD

extern const int amd_erratum_383[];

extern const int amd_erratum_400[];

extern bool cpu_has_amd_erratum(const int *);



#define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }

#define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }

#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \

	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))

#define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)

#define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)

#define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)



#else

#define cpu_has_amd_erratum(x)	(false)

#endif /* CONFIG_CPU_SUP_AMD */



#endif /* _ASM_X86_PROCESSOR_H */

arch/x86/include/asm/required-features.h

+2 −0
Original line number Diff line number Diff line
@@ -84,5 +84,7 @@ 
#define REQUIRED_MASK5	0

#define REQUIRED_MASK6	0

#define REQUIRED_MASK7	0

#define REQUIRED_MASK8	0

#define REQUIRED_MASK9	0



#endif /* _ASM_X86_REQUIRED_FEATURES_H */