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Commit e8c534ec authored by Michal Schmidt's avatar Michal Schmidt Committed by H. Peter Anvin
Browse files

x86: Fix keeping track of AMD C1E 



Accomodate the original C1E-aware idle routine to the different times
during boot when the BIOS enables C1E. While at it, remove the synthetic
CPUID flag in favor of a single global setting which denotes C1E status
on the system.

[ hpa: changed c1e_enabled to be a bool; clarified cpu bit 3:21 comment ]

Signed-off-by: default avatarMichal Schmidt <mschmidt@redhat.com>
LKML-Reference: <20100727165335.GA11630@aftab>
Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 9792db61

arch/x86/include/asm/acpi.h

+1 −1
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) 
	    boot_cpu_data.x86_model <= 0x05 &&

	    boot_cpu_data.x86_mask < 0x0A)

		return 1;

	else if (boot_cpu_has(X86_FEATURE_AMDC1E))

	else if (c1e_detected)

		return 1;

	else

		return max_cstate;

arch/x86/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ 
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */

#define X86_FEATURE_11AP	(3*32+19) /* "" Bad local APIC aka 11AP */

#define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */

#define X86_FEATURE_AMDC1E	(3*32+21) /* AMD C1E detected */

					  /* 21 available, was AMD_C1E */

#define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */

#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */

#define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */

arch/x86/include/asm/processor.h

+1 −0
Original line number Diff line number Diff line
@@ -762,6 +762,7 @@ extern void init_c1e_mask(void); 
extern unsigned long		boot_option_idle_override;

extern unsigned long		idle_halt;

extern unsigned long		idle_nomwait;

extern bool			c1e_detected;



/*

 * on systems with caches, caches must be flashed as the absolute

arch/x86/kernel/process.c

+5 −3
Original line number Diff line number Diff line
@@ -525,8 +525,10 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) 
	return (edx & MWAIT_EDX_C1);

}



bool c1e_detected;

EXPORT_SYMBOL(c1e_detected);



static cpumask_var_t c1e_mask;

static int c1e_detected;



void c1e_remove_cpu(int cpu)

{
@@ -548,12 +550,12 @@ static void c1e_idle(void) 
		u32 lo, hi;



		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);



		if (lo & K8_INTP_C1E_ACTIVE_MASK) {

			c1e_detected = 1;

			c1e_detected = true;

			if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))

				mark_tsc_unstable("TSC halt in AMD C1E");

			printk(KERN_INFO "System has AMD C1E enabled\n");

			set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);

		}

	}

drivers/acpi/processor_idle.c

+1 −1
Original line number Diff line number Diff line
@@ -164,7 +164,7 @@ static void lapic_timer_check_state(int state, struct acpi_processor *pr, 
	if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT))

		return;



	if (boot_cpu_has(X86_FEATURE_AMDC1E))

	if (c1e_detected)

		type = ACPI_STATE_C1;



	/*