Merge branches 'arnd-randcfg-fixes', 'debug', 'io' (early part), 'l2x0',...

* ARM L2 Cache Controller

ARM cores often have a separate level 2 cache controller. There are various

implementations of the L2 cache controller with compatible programming models.

The ARM L2 cache representation in the device tree should be done as follows:

Required properties:

- compatible : should be one of:

	"arm,pl310-cache"

	"arm,l220-cache"

	"arm,l210-cache"

- cache-unified : Specifies the cache is a unified cache.

- cache-level : Should be set to 2 for a level 2 cache.

- reg : Physical base address and size of cache controller's memory mapped

  registers.

Optional properties:

- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of

  read, write and setup latencies. Minimum valid values are 1. Controllers

  without setup latency control should use a value of 0.

- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of

  read, write and setup latencies. Controllers without setup latency control

  should use 0. Controllers without separate read and write Tag RAM latency

  values should only use the first cell.

- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.

- arm,filter-ranges : <start length> Starting address and length of window to

  filter. Addresses in the filter window are directed to the M1 port. Other

  addresses will go to the M0 port.

- interrupts : 1 combined interrupt.

Example:

L2: cache-controller {

        compatible = "arm,pl310-cache";

        reg = <0xfff12000 0x1000>;

        arm,data-latency = <1 1 1>;

        arm,tag-latency = <2 2 2>;

        arm,filter-latency = <0x80000000 0x8000000>;

        cache-unified;

        cache-level = <2>;

	interrupts = <45>;

};

	default y

	select HAVE_AOUT

	select HAVE_DMA_API_DEBUG

	select HAVE_IDE

	select HAVE_IDE if PCI || ISA || PCMCIA

	select HAVE_MEMBLOCK

	select RTC_LIB

	select SYS_SUPPORTS_APM_EMULATION

	  The base address of exception vectors.

config ARM_PATCH_PHYS_VIRT

	bool "Patch physical to virtual translations at runtime"

	bool "Patch physical to virtual translations at runtime" if EMBEDDED

	default y

	depends on !XIP_KERNEL && MMU

	depends on !ARCH_REALVIEW || !SPARSEMEM

	help

	  kernel in system memory.

	  This can only be used with non-XIP MMU kernels where the base

	  of physical memory is at a 16MB boundary, or theoretically 64K

	  for the MSM machine class.

	  of physical memory is at a 16MB boundary.

	  Only disable this option if you know that you do not require

	  this feature (eg, building a kernel for a single machine) and

	  you need to shrink the kernel to the minimal size.

config ARM_PATCH_PHYS_VIRT_16BIT

	def_bool y

	depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM

	help

	  This option extends the physical to virtual translation patching

	  to allow physical memory down to a theoretical minimum of 64K

	  boundaries.

source "init/Kconfig"

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select ARM_PATCH_PHYS_VIRT if MMU

	help

	  This enables support for systems based on the Atmel AT91RM9200,

	  AT91SAM9 and AT91CAP9 processors.

	select CPU_SA110

	select FOOTBRIDGE

	select GENERIC_CLOCKEVENTS

	select HAVE_IDE

	help

	  Support for systems based on the DC21285 companion chip

	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.

	select SPARSE_IRQ

	select AUTO_ZRELADDR

	select MULTI_IRQ_HANDLER

	select ARM_CPU_SUSPEND if PM

	select HAVE_IDE

	help

	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.

	select NO_IOPORT

	select ARCH_SPARSEMEM_ENABLE

	select ARCH_USES_GETTIMEOFFSET

	select HAVE_IDE

	help

	  On the Acorn Risc-PC, Linux can support the internal IDE disk and

	  CD-ROM interface, serial and parallel port, and the floppy drive.

	select HAVE_SCHED_CLOCK

	select TICK_ONESHOT

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_IDE

	help

	  Support for StrongARM 11x0 based boards.

		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \

		 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \

		 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE

	depends on MMU

	select USE_GENERIC_SMP_HELPERS

	select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP

	help

	  If you don't know what to do here, say Y.

config ARM_CPU_TOPOLOGY

	bool "Support cpu topology definition"

	depends on SMP && CPU_V7

	default y

	help

	  Support ARM cpu topology definition. The MPIDR register defines

	  affinity between processors which is then used to describe the cpu

	  topology of an ARM System.

config SCHED_MC

	bool "Multi-core scheduler support"

	depends on ARM_CPU_TOPOLOGY

	help

	  Multi-core scheduler support improves the CPU scheduler's decision

	  making when dealing with multi-core CPU chips at a cost of slightly

	  increased overhead in some places. If unsure say N here.

config SCHED_SMT

	bool "SMT scheduler support"

	depends on ARM_CPU_TOPOLOGY

	help

	  Improves the CPU scheduler's decision making when dealing with

	  MultiThreading at a cost of slightly increased overhead in some

	  places. If unsure say N here.

config HAVE_ARM_SCU

	bool

	help

	depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL

	select AEABI

	select ARM_ASM_UNIFIED

	select ARM_UNWIND

	help

	  By enabling this option, the kernel will be compiled in

	  Thumb-2 mode. A compiler/assembler that understand the unified

		CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE

	def_bool y

config ARM_CPU_SUSPEND

	def_bool PM_SLEEP

endmenu

source "net/Kconfig"

# These options are only for real kernel hackers who want to get their hands dirty.

config DEBUG_LL

	bool "Kernel low-level debugging functions"

	bool "Kernel low-level debugging functions (read help!)"

	depends on DEBUG_KERNEL

	help

	  Say Y here to include definitions of printascii, printch, printhex

	  in the kernel.  This is helpful if you are debugging code that

	  executes before the console is initialized.

config EARLY_PRINTK

	bool "Early printk"

	  Note that selecting this option will limit the kernel to a single

	  UART definition, as specified below. Attempting to boot the kernel

	  image on a different platform *will not work*, so this option should

	  not be enabled for kernels that are intended to be portable.

choice

	prompt "Kernel low-level debugging port"

	depends on DEBUG_LL

	config DEBUG_LL_UART_NONE

		bool "No low-level debugging UART"

		help

	  Say Y here if you want to have an early console using the

	  kernel low-level debugging functions. Add earlyprintk to your

	  kernel parameters to enable this console.

		  Say Y here if your platform doesn't provide a UART option

		  below. This relies on your platform choosing the right UART

		  definition internally in order for low-level debugging to

		  work.

	config DEBUG_ICEDCC

		bool "Kernel low-level debugging via EmbeddedICE DCC channel"

	depends on DEBUG_LL

		help

	  Say Y here if you want the debug print routines to direct their

	  output to the EmbeddedICE macrocell's DCC channel using

		  Say Y here if you want the debug print routines to direct

		  their output to the EmbeddedICE macrocell's DCC channel using

		  co-processor 14. This is known to work on the ARM9 style ICE

		  channel and on the XScale with the PEEDI.

	  It does include a timeout to ensure that the system does not

	  totally freeze when there is nothing connected to read.

		  Note that the system will appear to hang during boot if there

		  is nothing connected to read from the DCC.

config OC_ETM

	bool "On-chip ETM and ETB"

	select ARM_AMBA

	config DEBUG_FOOTBRIDGE_COM1

		bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"

		depends on FOOTBRIDGE

		help

	  Enables the on-chip embedded trace macrocell and embedded trace

	  buffer driver that will allow you to collect traces of the

	  kernel code.

		  Say Y here if you want the debug print routines to direct

		  their output to the 8250 at PCI COM1.

	config DEBUG_DC21285_PORT

		bool "Kernel low-level debugging messages via footbridge serial port"

	depends on DEBUG_LL && FOOTBRIDGE

		depends on FOOTBRIDGE

		help

		  Say Y here if you want the debug print routines to direct

		  their output to the serial port in the DC21285 (Footbridge).

	config DEBUG_CLPS711X_UART1

		bool "Kernel low-level debugging messages via UART1"

		depends on ARCH_CLPS711X

		help

	  Say Y here if you want the debug print routines to direct their

	  output to the serial port in the DC21285 (Footbridge). Saying N

	  will cause the debug messages to appear on the first 16550

	  serial port.

		  Say Y here if you want the debug print routines to direct

		  their output to the first serial port on these devices.

	config DEBUG_CLPS711X_UART2

		bool "Kernel low-level debugging messages via UART2"

	depends on DEBUG_LL && ARCH_CLPS711X

		depends on ARCH_CLPS711X

		help

	  Say Y here if you want the debug print routines to direct their

	  output to the second serial port on these devices.  Saying N will

	  cause the debug messages to appear on the first serial port.

		  Say Y here if you want the debug print routines to direct

		  their output to the second serial port on these devices.

endchoice

config EARLY_PRINTK

	bool "Early printk"

	depends on DEBUG_LL

	help

	  Say Y here if you want to have an early console using the

	  kernel low-level debugging functions. Add earlyprintk to your

	  kernel parameters to enable this console.

config OC_ETM

	bool "On-chip ETM and ETB"

	depends on ARM_AMBA

	help

	  Enables the on-chip embedded trace macrocell and embedded trace

	  buffer driver that will allow you to collect traces of the

	  kernel code.

config DEBUG_S3C_UART

	depends on PLAT_SAMSUNG

ifeq ($(CONFIG_ARCH_SA1100),y)

textofs-$(CONFIG_SA1111) := 0x00208000

endif

textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000

textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000

textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000

# Machine directory name.  This list is sorted alphanumerically

# by CONFIG_* macro name.

		return -EINVAL;

	mask = 0xff << shift;

	bit = 1 << (cpu + shift);

	bit = 1 << (cpu_logical_map(cpu) + shift);

	spin_lock(&irq_controller_lock);

	val = readl_relaxed(reg) & ~mask;

	unsigned int irq_start)

{

	unsigned int gic_irqs, irq_limit, i;

	u32 cpumask;

	void __iomem *base = gic->dist_base;

	u32 cpumask = 1 << smp_processor_id();

	u32 cpu = 0;

#ifdef CONFIG_SMP

	cpu = cpu_logical_map(smp_processor_id());

#endif

	cpumask = 1 << cpu;

	cpumask |= cpumask << 8;

	cpumask |= cpumask << 16;

#ifdef CONFIG_SMP

void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)

{

	unsigned long map = *cpus_addr(*mask);

	int cpu;

	unsigned long map = 0;

	/* Convert our logical CPU mask into a physical one. */

	for_each_cpu(cpu, mask)

		map |= 1 << cpu_logical_map(cpu);

	/*

	 * Ensure that stores to Normal memory are visible to the