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Commit 05b088b6 authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
Browse files

EDAC, altera: Move device structs and defines to the header 



Move the device structs and defines to altera_edac.h in preparation for
adding the Arria10 L2 cache ECC.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1458576106-24505-3-git-send-email-tthayer@opensource.altera.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 3a8f21f1

drivers/edac/altera_edac.c

+0 −43
Original line number Diff line number Diff line
@@ -78,27 +78,6 @@ static const struct altr_sdram_prv_data a10_data = { 
	.ue_set_mask        = A10_DIAGINT_TDERRA_MASK,

};



/************************** EDAC Device Defines **************************/



/* OCRAM ECC Management Group Defines */

#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04

#define ALTR_OCR_ECC_EN                 BIT(0)

#define ALTR_OCR_ECC_INJS               BIT(1)

#define ALTR_OCR_ECC_INJD               BIT(2)

#define ALTR_OCR_ECC_SERR               BIT(3)

#define ALTR_OCR_ECC_DERR               BIT(4)



/* L2 ECC Management Group Defines */

#define ALTR_MAN_GRP_L2_ECC_OFFSET      0x00

#define ALTR_L2_ECC_EN                  BIT(0)

#define ALTR_L2_ECC_INJS                BIT(1)

#define ALTR_L2_ECC_INJD                BIT(2)



#define ALTR_UE_TRIGGER_CHAR            'U'   /* Trigger for UE */

#define ALTR_TRIGGER_READ_WRD_CNT       32    /* Line size x 4 */

#define ALTR_TRIG_OCRAM_BYTE_SIZE       128   /* Line size x 4 */

#define ALTR_TRIG_L2C_BYTE_SIZE         4096  /* Full Page */



/*********************** EDAC Memory Controller Functions ****************/



/* The SDRAM controller uses the EDAC Memory Controller framework.       */
@@ -571,28 +550,6 @@ module_platform_driver(altr_edac_driver); 
const struct edac_device_prv_data ocramecc_data;

const struct edac_device_prv_data l2ecc_data;



struct edac_device_prv_data {

	int (*setup)(struct platform_device *pdev, void __iomem *base);

	int ce_clear_mask;

	int ue_clear_mask;

	char dbgfs_name[20];

	void * (*alloc_mem)(size_t size, void **other);

	void (*free_mem)(void *p, size_t size, void *other);

	int ecc_enable_mask;

	int ce_set_mask;

	int ue_set_mask;

	int trig_alloc_sz;

};



struct altr_edac_device_dev {

	void __iomem *base;

	int sb_irq;

	int db_irq;

	const struct edac_device_prv_data *data;

	struct dentry *debugfs_dir;

	char *edac_dev_name;

};



static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)

{

	irqreturn_t ret_value = IRQ_NONE;

drivers/edac/altera_edac.h

+44 −0
Original line number Diff line number Diff line
@@ -195,4 +195,48 @@ struct altr_sdram_mc_data { 
	const struct altr_sdram_prv_data *data;

};



/************************** EDAC Device Defines **************************/

/***** General Device Trigger Defines *****/

#define ALTR_UE_TRIGGER_CHAR            'U'   /* Trigger for UE */

#define ALTR_TRIGGER_READ_WRD_CNT       32    /* Line size x 4 */

#define ALTR_TRIG_OCRAM_BYTE_SIZE       128   /* Line size x 4 */

#define ALTR_TRIG_L2C_BYTE_SIZE         4096  /* Full Page */



/******* Cyclone5 and Arria5 Defines *******/

/* OCRAM ECC Management Group Defines */

#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04

#define ALTR_OCR_ECC_EN                 BIT(0)

#define ALTR_OCR_ECC_INJS               BIT(1)

#define ALTR_OCR_ECC_INJD               BIT(2)

#define ALTR_OCR_ECC_SERR               BIT(3)

#define ALTR_OCR_ECC_DERR               BIT(4)



/* L2 ECC Management Group Defines */

#define ALTR_MAN_GRP_L2_ECC_OFFSET      0x00

#define ALTR_L2_ECC_EN                  BIT(0)

#define ALTR_L2_ECC_INJS                BIT(1)

#define ALTR_L2_ECC_INJD                BIT(2)



struct edac_device_prv_data {

	int (*setup)(struct platform_device *pdev, void __iomem *base);

	int ce_clear_mask;

	int ue_clear_mask;

	char dbgfs_name[20];

	void * (*alloc_mem)(size_t size, void **other);

	void (*free_mem)(void *p, size_t size, void *other);

	int ecc_enable_mask;

	int ce_set_mask;

	int ue_set_mask;

	int trig_alloc_sz;

};



struct altr_edac_device_dev {

	void __iomem *base;

	int sb_irq;

	int db_irq;

	const struct edac_device_prv_data *data;

	struct dentry *debugfs_dir;

	char *edac_dev_name;

};



#endif	/* #ifndef _ALTERA_EDAC_H */