Merge "clk: qcom: Update the source clock for 24MHz MCLK" (fb2e8b97) · Commits · e / devices / android_kernel_sony_msm8998

drivers/clk/qcom/mmcc-sdm660.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1041,7 +1041,7 @@ static const struct freq_tbl ftbl_mclk0_clk_src[] = {
		F(9600000, P_CXO, 2, 0, 0),
		F(16666667, P_GPLL0_OUT_MAIN_DIV, 2, 1, 9),
		F(19200000, P_CXO, 1, 0, 0),
		F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25),
		F(24000000, P_MMPLL10_PLL_OUT_MAIN, 1, 1, 24),
		F(33333333, P_GPLL0_OUT_MAIN_DIV, 1, 1, 9),
		F(48000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
		F(66666667, P_GPLL0_OUT_MAIN, 1, 1, 9),