Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 888f9aac authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: Update the source clock for 24MHz MCLK 



The source clock of MMPLL10 has better jitter specs for MCLK than GPLL0_DIV
clock, so update the same to obtain 24MHz clock.

Change-Id: I57a77a83a5028c85d82fda4af53732f0bfb263e7
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 796d604a

drivers/clk/qcom/mmcc-sdm660.c

+1 −1
Original line number Diff line number Diff line
@@ -1041,7 +1041,7 @@ static const struct freq_tbl ftbl_mclk0_clk_src[] = { 
	F(9600000, P_CXO, 2, 0, 0),

	F(16666667, P_GPLL0_OUT_MAIN_DIV, 2, 1, 9),

	F(19200000, P_CXO, 1, 0, 0),

	F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25),

	F(24000000, P_MMPLL10_PLL_OUT_MAIN, 1, 1, 24),

	F(33333333, P_GPLL0_OUT_MAIN_DIV, 1, 1, 9),

	F(48000000, P_GPLL0_OUT_MAIN, 1, 2, 25),

	F(66666667, P_GPLL0_OUT_MAIN, 1, 1, 9),