Merge "ARM: dts: msm: add the dtsi entries for DP PLL clocks for msm8998" (ec03d773) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm/boot/dts/qcom/msm8998-mdss.dtsi

+6 −2

Original line number	Diff line number	Diff line
		@@ -497,12 +497,16 @@
		<&clock_mmss clk_mmss_mdss_dp_link_clk>,
		<&clock_mmss clk_mmss_mdss_dp_link_intf_clk>,
		<&clock_mmss clk_mmss_mdss_dp_crypto_clk>,
		<&clock_mmss clk_mmss_mdss_dp_pixel_clk>;
		<&clock_mmss clk_mmss_mdss_dp_pixel_clk>,
		<&mdss_dp_pll clk_vco_divided_clk_src_mux>,
		<&mdss_dp_pll clk_vco_divsel_two_clk_src>,
		<&mdss_dp_pll clk_vco_divsel_four_clk_src>;
		clock-names = "core_mnoc_clk", "core_iface_clk", "core_bus_clk",
		"core_mdp_core_clk", "core_alt_iface_clk",
		"core_aux_clk", "core_ref_clk_src", "core_ref_clk",
		"ctrl_link_clk", "ctrl_link_iface_clk",
		"ctrl_crypto_clk", "ctrl_pixel_clk";
		"ctrl_crypto_clk", "ctrl_pixel_clk", "pixel_parent",
		"pixel_clk_two_div", "pixel_clk_four_div";

		qcom,dp-usbpd-detection = <&pmi8998_pdphy>;

+26 −0

Original line number	Diff line number	Diff line
		@@ -422,6 +422,22 @@ static int mdss_dp_clk_init(struct mdss_dp_drv_pdata *dp_drv,
		__func__);
		dp_drv->pixel_parent = NULL;
		}

		dp_drv->pixel_clk_two_div = devm_clk_get(dev,
		"pixel_clk_two_div");
		if (IS_ERR(dp_drv->pixel_clk_two_div)) {
		pr_debug("%s: Unable to get DP pixel two div clk\n",
		__func__);
		dp_drv->pixel_clk_two_div = NULL;
		}

		dp_drv->pixel_clk_four_div = devm_clk_get(dev,
		"pixel_clk_four_div");
		if (IS_ERR(dp_drv->pixel_clk_four_div)) {
		pr_debug("%s: Unable to get DP pixel four div clk\n",
		__func__);
		dp_drv->pixel_clk_four_div = NULL;
		}
		} else {
		if (dp_drv->pixel_parent)
		devm_clk_put(dev, dp_drv->pixel_parent);
		@@ -1418,6 +1434,16 @@ static int mdss_dp_enable_mainlink_clocks(struct mdss_dp_drv_pdata *dp)
		return ret;
		}

		if (dp->pixel_parent && dp->pixel_clk_two_div &&
		dp->pixel_clk_four_div) {
		if (dp->link_rate == DP_LINK_RATE_540)
		clk_set_parent(dp->pixel_parent,
		dp->pixel_clk_four_div);
		else
		clk_set_parent(dp->pixel_parent,
		dp->pixel_clk_two_div);
		}

		mdss_dp_set_clock_rate(dp, "ctrl_link_clk",
		(dp->link_rate * DP_LINK_RATE_MULTIPLIER) / DP_KHZ_TO_HZ);

+2 −0

Original line number	Diff line number	Diff line
		@@ -614,6 +614,8 @@ struct mdss_dp_drv_pdata {
		/* DP Pixel clock RCG and PLL parent */
		struct clk *pixel_clk_rcg;
		struct clk *pixel_parent;
		struct clk *pixel_clk_two_div;
		struct clk *pixel_clk_four_div;

		/* regulators */
		struct dss_module_power power_data[DP_MAX_PM];