Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4f10d5d0 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
Browse files

ARM: dts: msm: add the dtsi entries for DP PLL clocks for msm8998 



The parent of DP VCO divided mux clock needs to be set from the
Display Port driver based on the link rate. Add the dtsi entries
needs for this support for msm8998.

Change-Id: I76c2568579735f20106e40a359fd0052a2f51fbf
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent 54d865e4

arch/arm/boot/dts/qcom/msm8998-mdss.dtsi

+6 −2
Original line number Diff line number Diff line
@@ -497,12 +497,16 @@ 
			 <&clock_mmss clk_mmss_mdss_dp_link_clk>,

			 <&clock_mmss clk_mmss_mdss_dp_link_intf_clk>,

			 <&clock_mmss clk_mmss_mdss_dp_crypto_clk>,

			 <&clock_mmss clk_mmss_mdss_dp_pixel_clk>;

			 <&clock_mmss clk_mmss_mdss_dp_pixel_clk>,

			 <&mdss_dp_pll clk_vco_divided_clk_src_mux>,

			 <&mdss_dp_pll clk_vco_divsel_two_clk_src>,

			 <&mdss_dp_pll clk_vco_divsel_four_clk_src>;

		clock-names = "core_mnoc_clk", "core_iface_clk", "core_bus_clk",

			"core_mdp_core_clk", "core_alt_iface_clk",

			"core_aux_clk", "core_ref_clk_src", "core_ref_clk",

			"ctrl_link_clk", "ctrl_link_iface_clk",

			"ctrl_crypto_clk", "ctrl_pixel_clk";

			"ctrl_crypto_clk", "ctrl_pixel_clk", "pixel_parent",

			"pixel_clk_two_div", "pixel_clk_four_div";



		qcom,dp-usbpd-detection = <&pmi8998_pdphy>;